Method on scan chain reordering for lowering VLSI power...

Details Method on scan chain reordering for lowering VLSI power... Method on scan chain reordering for lowering VLSI power...

2007-02-20

2007-02-20

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10827507

ABSTRACT:
A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method includes embedding a developed tool into an existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics quickly judge if the problem has corresponding feasible solutions and searching the optimal solution. Modified data from the given scan chain declaration data and the scan pattern data, which satisfy the constraints, can be obtained.

REFERENCES:
patent: 6272668 (2001-08-01), Teene
patent: 6282506 (2001-08-01), Takeoka et al.
patent: 6662327 (2003-12-01), Rajski
patent: 6986090 (2006-01-01), Hathaway et al.
patent: 2004/0177299 (2004-09-01), Wang et al.
patent: 2005/0010832 (2005-01-01), Caswell et al.

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