Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-09-21
2004-12-21
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
06834366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to a semiconductor memory, and more particularly, to a method for selectively outputting internal information of a semiconductor memory without adding output pins, as well as a circuit for selectively outputting such internal information.
2. Description of Related Art
As a consequence of the increasing density of circuit devices in a semiconductor chip due to improvements in circuit design and methods for fabricating semiconductor devices, the testing of various electrical characteristics and functional characteristics of circuit devices in a chip by using built in self test (BIST) methods will become increasingly important. Indeed, to enhance production yield, testing is necessary to determine whether there are defects in a chip or for analyzing failed portions in a chip and, thereby, provide feedback to the fabricating processes. As the integration density increases, however, the effective testing becomes increasingly difficult and, consequently, the cost for such tests increases.
To mitigate the problems associated with testing circuits comprising high integration density, functional modules are formed by assembling integrated circuits and graded system design has been developed to form a system by combination of the modules. Accordingly, board or system level testing has evolved to require a more systematic design for testability (DFT). In order to meet such requirement, a boundary scan design that has been studied by Joint Test Action Group (JTAG) in the late 1980's was standardized according to IEEE in 1990. The JTAG standard, which has been widely used in this field, is defined by IEEE 1149.1, IEEE standard test access port and boundary scan architecture. The IEEE standard 1149.1 is disclosed in the reference “IEEE computer society press, 1990” which defines test access port and boundary scan architecture.
To solve node access problems or all node test problems that are created during testing of a system board consisting of surface mount, tape automated bonding, miniaturized components, multi chip module (MCM), complex ASICs, etc., IEEE suggests standards of device manufacturing and loaded circuit board testing, which is called Joint Test Action Group (JTAG).
Generally, the JTAG logic is employed for testing a semiconductor memory chip such as static random access memory (SRAM) using a ball grid array (BGA). In the SRAM, when performing the boundary scan test wherein a shift resistor is provided between each of the device pins and internal logic, currently, the only testing that is performed is whether a short and open in each of pins is created. The reason is that the signal delay and the overhead associated with chip size are created when all the JTAG IEEE 1149.1 standards are used in an SRAM.
Generally, the test circuit such as the JTAG logic is operated in a specific operation mode, for example, a test mode, not in a normal mode in which a semiconductor memory chip is normally operated. Accordingly, the test circuit serves to check for potential defects of a chip in a test mode only, but cannot check the operation state of the chip during a normal mode of operation.
Designers and users of semiconductor memories, however, desire to monitor the state of each of the signals in a chip during normal operation of the chip, and not just testing the chip in a test mode. Indeed, if a designer can obtain internal information of a chip at an early stage of development of a memory product, each of the functional blocks of the semiconductor memory can be effectively evaluated, which can lead to a reduction of the development period. Moreover, users may desire to check the internal timing delay and the internal reference voltage of peripheral circuits provided in a semiconductor memory so as to effectively apply the semiconductor memory in a desired system. For example, a user may require adding an option to a semiconductor memory having a high-speed interface, by which internal reference voltage and data sampling clock, etc. can be controlled by an external digital signal.
It is therefore highly desirable to provide a testing function that allows a user, for example, to check internal information of a chip during a normal mode of operation. It is very difficult, however, to assign additional package pins to the semiconductor memory chip without any preparations. The reason is that it is even difficult, in the first instance, to arrange the package pins that are needed in memory operation of a highly integrated semiconductor memory having a relatively fixed package size. As a result, the integration density of semiconductor memory tends to increase rapidly, but it is a very critical problem to assign package pins to the semiconductor memory because package size is difficult to change. Therefore, it is desirable to minimize the number of test pins that do not directly relate to the operation of semiconductor memory, relative to the insufficient assignment of package pins.
With the conventional technique, it is difficult to monitor the internal state of chip as a test circuit fabricated for test with an external package pin because of such a lack of a phenomenon in pin assignment when the chip normally operates. Thus, anticipation evaluation has been performed through simulation thereby decreasing reliability in test of the internal information.
As described above, in the conventional technique, because of the difficulty in separately assigning package pins that output internal information in a normal operation of chip, a disadvantage is that the internal state of a chip cannot be exactly monitored. Accordingly, an improved technique for accurate monitoring the states of various internal signals during a normal mode of operation without the addition of package pins, is highly desirable.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved technique by which the aforementioned problems can be solved.
It is another object of the present invention to provide a circuit and a method for accurately monitoring the state of various internal signals that are generated in a normal operation of chip using a smaller number of pins than in the conventional techniques.
It is yet another object of the present invention to provide a selective output method and an output circuit therefor by which internal information can be externally output through conventional test pins in a normal operation mode of a semiconductor memory.
It is another object of the present invention to provide a method for selectively outputting internal information of a semiconductor chip, and an output circuit therefore, wherein information relating to an internal power voltage or a reference power voltage of a semiconductor memory, for example, can be externally output as an analog signal without having to add additional output pins for such testing.
It is yet a further object of the present invention to provide an output circuit by which internal information of a semiconductor memory can be externally monitored during a normal operation of a chip.
It is another object of the invention to enable a user or designer to directly monitor various types of internal information during normal operation of a semiconductor chip without adding package pins, so as to improve testing reliability.
To achieve these objects, a method according to one aspect of the invention for outputting internal information in a semiconductor memory comprises the step of selectively outputting internal information through a test pin of a test circuit during a normal operation mode of the semiconductor memory.
In another aspect of the invention, an output circuit for outputting internal information of a semiconductor memory device comprising a test circuit, comprises:
an output terminal;
an output buffer for outputting test data that is generated by the semiconductor memory when the test circuit operates in a test mode;
an analog signal transmitter for providing the output terminal with analog internal information th
Kim Nam-Seog
Lee Kwang-Jin
F. Chau & Associates LLC
Lamarre Guy J.
Trimmings John P.
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