Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-11
2001-12-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06327684
ABSTRACT:
The present invention relates to methods and apparatus for testing digital systems including integrated circuits and, more specifically, to built-in self testing of integrated circuits having multiple clock domains with asynchronous clocks and non-integer frequency ratios.
BACKGROUND OF THE INVENTION
Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scanable memory elements of the system, capturing the response of the elements to the test stimulus, shifting the test response out of the system and then comparing the response to the response which should have been obtained if the system was operating according to design. Difficulties arise when signals cross the boundary between clock domains having different clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Otherwise, the test response from the system will not be repeatable and test results will be unreliable. The problem is especially severe in built-in self-test systems.
Methods have been developed for testing systems in which the ratio of the frequencies of two clock domains is an integer. However, it is not uncommon for digital systems to employ asynchronous clocks whose frequencies are not multiples of each other. For example, one clock domain could employ a clock rate of 200 MHz and other domain could employ a clock rate of 78 MHz, resulting in a non-integer frequency ratio of 2.564 . . . Solutions have yet to be developed for clock domains having non-integer frequency ratios. Testing of such systems using the functional system clocks is difficult because the phase relationship between the system clocks is not known and is variable over time. The term “functional system clock” refers to the normal operating frequency of a digital system or portion thereof. In order to achieve very high reliability circuits, it is essential that all clock domains be tested at full-speed.
Heretofore, such circuits have been tested by using test clock rates that are essentially the same as the functional clock rates but disabling all signal paths crossing clock domain boundaries and repeating the test for each clock domain. The primary drawbacks of this approach are that part of the logic is not tested and a series of tests must be performed in order to test all parts of the system. However, even then, it is not possible to obtain results for all parts of the system operating concurrently at speed.
It is also known to use test clock rates that are as close as possible to those of the functional clocks without exceeding the functional clock rates and that are multiples of each other. This is done by using the fastest functional clock as the test clock for the domain with the fastest clock rate and generating the test clocks required by other clock domains from the main test clock signal using a simple clock divider. For example, in a system having one clock domain with a functional clock frequency of 200 MHz and another clock domain with a clock frequency of 78 MHz, test clock rates of 200 MHz and 50 MHz would be used for testing. Nadeau-Dostie et al U.S. Pat. No. 5,349,587 granted on Sep. 20, 1994 for “Multiple Clock Rate Test Apparatus for Testing Digital Systems” and Bhawmik U.S. Pat. No 5,680,543 granted on Oct. 21, 1997 for “Method and Apparatus for Built-In Self-Test With Multiple Clock Circuits” illustrate the latter approach. Clearly, the primary drawback of this approach is that one of the clock domains is not tested at its full-speed (78 MHz).
It is also possible to combine the above methods sequentially. The drawbacks of this approach are longer test times, more complex test circuitry than is desirable and the inability of simultaneously or concurrently testing all components at their functional clock rates.
Thus, there is a need for testing method and circuitry which enables the testing at the design or functional speed of digital systems having two or more clock domains with asynchronous clocks whose frequencies are not multiples of one another.
SUMMARY OF THE INVENTION
One aspect of the present invention provides a scan-based method of testing a digital system, the method including a sequence of test operations including a shift-in operation in which a test stimulus is shifted into scanable memory elements in the system, a capture operation in which data in said memory elements is captured, and a shift-out operation in which captured data is shifted out of said core logic for analysis, the method comprising, for each said operation, concurrently enabling the domain clock of each clock domain in the system at the beginning of each test operation; performing the test operation in each domain; and disabling the domain clock at the end of each test operation in each domain.
The test method allows test vectors to be applied and responses to be extracted at-speed within each clock domain and the structural interface between the clock domains to be tested at-speed. The test signature obtained from the circuit when tested in this manner does not change even if the system clock frequencies change and the test signature and fault coverage can be computed using a fast combinational fault simulator in a single operation because the test controllers provided to implement the method can be programmed such that they appear to be a single test controller.
A further advantage of the method is that it allows a system to be tested using a tester that cannot provide the exact frequencies used during normal operation of the system or that can provide only one high-speed clock for initial manufacturing of the circuit and yet still obtain the same test signature. This considerably simplifies test data management.
Still further, the method also allows the timing between clock domains to be made robust to make the circuit response repeatable. The verification of the timing during the test mode is simple.
The method is able to accommodate an arbitrary number of asynchronous clock domains and the circuitry to accommodate them is readily scalable.
Still further, the method of the present invention can readily handle another problem which has plagued circuit designers and that is the problem posed by circuits having multi-cycle paths. Multi-cycle paths result when more than one clock cycle is required for a signal to propagate from the output of one memory element to the input of another. Many test methods do not accommodate multi-cycle paths and therefore may produce invalid test results.
Another aspect of the present invention involves the provision test circuitry for performing the method of the present invention. The present invention provides an on-chip self-synchronizing test controller for each frequency domain. Each controller employs a generic asynchronous hand-shaking protocol to synchronize test operations in such a manner that the circuit test responses are inherently repeatable.
Each test controller disables its domain output clock at the end of a test operation, generates a clock disabled signal and applies the signal to all test controllers, and then waits for other controllers to do the same. The clock controller does not re-enable its clock until it has received a corresponding clock disabled signal from all of the other test controllers. Thus, controllers with fast clocks complete their respective phase of a test operation before controllers with slower clock rates and then simply wait for the other controllers to catch up. The next operation in the sequence of operations is started in all clock domains when all controllers have completed their phase of the test. This allows elements at opposite ends of cross-boundary signal paths to be synchronized and the required number of clock cycles to be executed for elements located on multi-cycle path signals.
Accordingly, another aspect of the present invention provides a clock controller for use in a test controller
Cote Jean-Francois
Hasani Naader
Nadeau-Dostie Benoit
De'cady Albert
LogicVision, Inc.
Sheridan & Ross P.C.
Torres Joseph D.
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