Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-29
2003-07-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000, C714S720000, C345S551000
Reexamination Certificate
active
06601205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods of addressing in memory circuits and, more particularly, to a method which simplifies the testing of memory circuits by overcoming the mapping problems between physical and logical data patters (i.e., data scrambling).
2. Background Description
In a memory circuit (e.g., a Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like), data is normally stored in a matrix of memory elements. The data values of the memory elements can be accessed (read operation) or modified (write operation) exclusively by using the interface of the memory circuit. During a read command, an address is supplied to this interface. Then, this address is processed by the memory circuit and the data located at this address is delivered to the data output. In contrast, a write command stores externally provided data at the address supplied in conjunction with the data.
Therefore, a memory circuit exhibits two types of memory addressing. One address describes the physical location of a storage element (referred to as the “physical address”). The other address is the address that has to be provided to the interface of the memory circuit in order to access a specific storage element (referred to as the “logical address”). In prior memory generations the relation between the physical and the logical addresses was simple, because the two portions of the logical address (typically called row and column) had a transparent relation to the x and y-coordinates of the storage elements (i.e., the physical address).
However, modem architectures of memory circuits increasingly obstruct the extraction of a transparent mapping scheme between the logical and the physical addresses. The non-trivial mappings are summarized by the term “data scrambling”. Generally, data scrambling can be caused by several factors, including:
bit line twisting,
word line addressing and segmentation,
layout mirroring,
multiplexing and de-multiplexing of data packages in the burst modes, and
wrap type dependency (interleaved versus sequential).
The combination of these data scramblings makes it nearly impossible to derive a logical address for a given physical address. However, this is a prerequisite for hardware testing, since the storage elements of a memory matrix are solely accessible through the interface of the memory circuit. In particular, several characteristic physical data patterns, like stripes, checker board, blankets, etc., are executed for a memory matrix in order to identify problems caused by coupling and substrate noise. Furthermore, hardware testing must be able to extract the physical location of failures when the data at the logical interface is incorrect.
Taking into account the size of current memory circuits, it is obvious that test pattern generation and analysis has to be performed automatically. However, currently used pattern generation techniques (based on procedural programming) are inefficient because the development of the underlying generation algorithm is obstructed by the data scrambling.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an automatic pattern generation and analysis method for performing hardware testing of memory circuits.
According to the invention, there is provided an automatic generation of a logical hardware test pattern based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.
The practice of the invention requires the following elements:
A pattern viewer and generator which represents a graphical user interface (GUI). This interface enables a graphical definition of the values stored in the memory elements. Furthermore, it provides a library with predefined standard pattern, like checker boards. Besides definition of pattern, this module also allows viewing the pattern stored in the memory circuit.
A layout of the memory matrix (or array). This portion is derived from the memory design. Basically, it provides the geometrical location (i.e., the x and y-coordinates) of each storage element.
A flattened array netlist (typically generated by a layout versus schematic tool) delivers a link between the hierarchical name of each storage element and its geometrical location.
A hierarchical representation of the memory circuit (netlist) which can be executed by a logic simulator.
A logic simulator allows modeling the behavior of the memory circuit by executing read and write commands on the netlist. Additionally, it provides a functionality to set initial conditions on circuit nodes (like the voltages of storage elements) before a simulation is started. Likewise, a functionality is supported which reads the final conditions of circuit nodes at the end of the simulation.
A pattern server (and/or a tester RAM) acts as an intermediate storage between the hardware tester and the logic simulator. Data is exchanged in pairs of address and data, simply describing the data value(s) stored at a specific logical address.
A hardware tester generates and measures electrical signals at the pins of the memory device.
A bit map analyzer can compare physical data patterns. Mismatches between an input pattern and the derived pattern can be analyzed.
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Frankowsky Gerd
Hsu Louis
Lehmann Gunther
Reith Armin
Braden Stanton
De'cady Albert
Infineon - Technologies AG
Torres Joseph D.
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