Method of repairing integrated circuits

Details Method of repairing integrated circuits Method of repairing integrated circuits

2000-06-21

2004-02-24

Decady, Albert (Department: 2123)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S010000, C714S733000

Reexamination Certificate

active

06697979

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an arrangement and method for repairing an integrated circuit.
BACKGROUND INFORMATION
German Patent Application No. 196 51 075.9-53 describes processors having a plurality of 2-dimensional or multidimensional arithmetic and logic units/cells. The computing power of such processors increases with the number of arithmetic and logic units present. Therefore, an attempt is made to integrate as many arithmetic and logic units as possible on one chip, which increases the area required. With an increase in area, there is also a higher probability of a chip having a manufacturing defect making it useless. All arithmetic and logic units arranged in matrix form have this problem, e.g., including other known types such as DPGAs, Kress arrays, systolic processors and RAW machines; likewise, some digital signal processors (DSPs) having more than one arithmetic and logic unit.
At the same time, all the aforementioned types require a great deal of testing, i.e., to detect faults, an especially large number of test cases must be generated and tested with respect to the functioning of the cells and the networking. Conventional methods such as BIST, boundary scan, etc. are difficult to integrate because of the large number of test vectors and they are also too time consuming and take up too much space.
Standard processors such as the x86 series, MIPS or ALPHA have a plurality of arithmetic and logic units which are driven at the same time by a VLIW command or with a time offset. In the future, the number of integrated units (integer units) and floating point units will continue to increase. Each unit must be tested adequately and must be largely free of defects.
Due to the increasing probability of defects with large chips, either only a very small number of cells can be integrated or production costs will increase greatly due to the resulting rejects. Very large chips will reach a maximum area beyond which a functional chip can no longer be produced. Due to the time consumed in testing according to conventional methods, there is a great increase in testing costs. Integrated BIST functions (built-in self-test) take up a great deal of area due to the high extra complexity, driving costs even higher and reducing manufacturing feasibility. In addition, this greatly increases the probability of a defect lying not within the actual function units but instead within the test structures.
Due to the increasing number of arithmetic and logic units, there is also an increase in the probability of defects. This means more rejects, causing manufacturing costs to increase. With an increase in area and a related increase in the number of transistors used, there is also an increase in probability of failure during use.
With regard to testing complexity and implementation of BIST, the discussion above regarding “multidimensional arrays of arithmetic and logic units” also applies here.
SUMMARY OF THE INVENTION
The present invention provides for replacing defective cells with functional cells and reducing rejects. A cell can be replaced either by the test systems at the time of manufacture of the chips or even by the user in the completely assembled system. Test vectors can be generated according to the BIST principle within the chip, or outside the unit according to a new method to save on space and costs. In addition, a possibility of chips automatically repairing defects without requiring any additional external tool is described. All the tests and repairs can be performed during operation of the chips.
An additional PAE not used in normal operation (referred to below as PAER) is assigned to a group of cells which are referred to below as PAEs according to German Patent 196 51 075.9-53. The cells may be arithmetic and logic units of any type, configurable (programmable) logic cells or other cores having any desired function. Grouping of the PAEs in rows or columns is preferred in the grouping of PAEs and allocation of the PAER, because this simplifies the networking. With respect to future chip technologies, reference is made to a possible grouping of the PAEs within a 3
rd
dimension. Multiplexers are connected upstream from the inputs of the PAEs in such a way that the input of the first PAE in the row/column can also be switched to the input of the second PAE in the row/column, and then the input of the second PAE can be switched to the input of the third PAE and so forth. The input of the last PAE is switched to the input of the PAER. This means that if there is a defect in the first PAE, its function is replaced by the second PAE, the function of the second is replaced by the third and so forth, until the function of the last PAE is replaced by the PAER. If a PAE within the column/row is defective, the PAEs upstream from it are switched normally and after the position of the defective PAE, all functions are shifted by one PAE. For example, if PAE
4
is defective, then PAEs
1
. . .
3
execute their respective functions, while the input multiplexer of PAE
5
is switched so that it receives the data of PAE
4
, the input multiplexer of PAE
6
receives the data of PAE
5
and so forth until the input of the PAER receives the data of the last PAE.
To supply the results back to the network in the proper sequence, multiplexers are also provided at the outputs of the PAEs, with the output multiplexer of PAE
1
either switching PAE
1
to the bus (if it is not defective) or if there is a defect, switching the output of PAE
2
to the bus, PAE
3
is switched to the bus instead of PAE
2
, until the last PAE, where the PAER is switched in its place. If the defective PAE is in the middle of the row/column, the outputs are shifted exactly as already described above for the inputs.
Especially with a configurable logic and configurable arithmetic and logic units, there are additional bus systems to transfer the configuration data and control the configuration. These bus systems are also connected by multiplexers in the same way as the buses mentioned in this section. The same thing is also true of bus systems over which commands are written to the respective arithmetic and logic units with a matrix arrangement of arithmetic and logic units (e.g., systolic processors, SIMD, etc.). Basically any bus or any signal can be sent over multiplexers. Depending on the fault tolerance requirements, the clock signal, for example, can be sent over multiplexers to prevent a possible short circuit, or the clock signal may be sent directly to the cell because such a failure need not be compensated. The fault tolerance step can be defined in the structural details according to the requirements for each signal or each bus individually.
The concept of correcting faults within gate structures may also be applied to bus systems in which an additional bus (BUS R) is assigned to a number of buses (BUS
1
. . . BUS n). If one of the buses is defective (BUS d), its function is assumed by one of its neighboring buses (BUS (d+1)). The function of the neighboring bus (BUS (d+1)) is assumed by its neighboring bus (BUS (d+2)), etc., with the direction of the bus assuming the function always remaining the same until the function of BUS n is assumed by BUS R.
When multiplexer structures are used with bus systems, the usual multiplexers, decoders and gates, tristate gates or bidirectional multiplexers are used according to the prevailing connection structure and the direction of the data.
Two groups of successive multiplexers should always assume the same state, i.e., MUX
1
=MUX
2
=MUX
3
=. . . =MUX n=state A, and MUX (n+1)=MUX (n+2)=MUX (n+3) . . . =MUX m=state B.
If no PAE is defective, then MUX
1
=MUX
2
=. . . MUX m=state A.
If the first PAE is defective, then MUX
1
=MUX
2
=. . . =MUX m=state B.
For example, if PAE
3
is defective, then MUX
1
=MUX
2
=state A, MUX
3
=MUX
4
=. . . =MUX m=state

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