Method tester and circuit for applying a pulse trigger to a unit

Details Method tester and circuit for applying a pulse trigger to a unit Method tester and circuit for applying a pulse trigger to a unit

1996-10-10

1999-11-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

059833785

ABSTRACT:
A unit (108) to be triggered, for example a memory, receives data under the control of Boundary Scan Test (BST) logic, via a BST chain (110). The invention utilizes a pulse circuit (202) which generates a pulse trigger for the unit (108) on the basis of a stimulus presented via the BST chain (110). This saves time, because it is no longer necessary to supply the entire pulse trigger via the BST chain and the supply of the stimulus now suffices.

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patent: 5648973 (1997-07-01), Mote, Jr.
"IEEE Standard Test Access Port and Boundary-Scan Architecture" IEEE STD 1149.1-1990; May 21, 1990.
"The ABCs of Boundary-Scan Test", Philips Test & Measurement, Eindhoven, The Netherlands, pp. 1-44.
"Boundary-Scan Test--A Practical Approach", Harry Bleeker, Peter Van Den Eijnden, Frans De Jong, pp. 156-166.

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