IC with expected data memory coupled to scan data register
IC with external register present lead connected to...
IC with internal interface switch for testability
IC with IP core and user-added scan register
IC with JTAG port, linking module, and off-chip TAP interface
IC with latching and switched I/O buffers
IC with protocol selection memory coupled to serial scan path
IC with protocol selection memory coupled to serial scan path
IC with scan distributor and scan collector circuitry
IC with separate scan paths and shift states
IC with serial scan path, protocol memory, and event circuit
IC with shared scan cells selectively connected in scan path
IC with TAP, STP and lock out controlled output buffer
IC with test cells having separate data and test paths
IDDQ test solution for large asics
Identification and test generation for primitive faults
Identifying bitstream load issues in an integrated circuit
Identifying faulty programmable interconnect resources of...
IEEE 1149.1 and P1500 test interfaces combined circuits and...
IEEE 1149.1 and P1500 test interfaces combined circuits and...