Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-14
2006-03-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07013415
ABSTRACT:
A semiconductor integrated circuit which is provided with a shift scan path incorporated in each function module and a testing I/O terminal connected to a shift scan path and provided separately from a normal-operation-use I/O terminal, and which comprises, all formed on one semiconductor chip, a bus interface circuit for connecting normal-operation-use I/O terminals of a plurality of function modules to a bus, an external interface switching circuit which switches between the bus-side I/O terminal of the bus interface circuit and the testing I/O terminal of each function module for connection to an external terminal and an interface control circuit for switch-controlling the external interface switching circuit.
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IEEE Standard 1149.1-1990 “IEEE Standard Test Access Port and Boundary-Scan Architecture”.
Kamei Tatsuya
Nishimoto Junichi
Tatezawa Ken
De'cady Albert
Hitachi ULSI Systems Co. Ltd.
Trimmings John P.
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