Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-19
2003-12-02
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
06658615
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to testing of integrated circuits having embedded cores and, more particularly, to a core design that efficiently supports a user-added scan register option.
BACKGROUND OF THE INVENTION
Rapid design and deployment of high complexity integrated circuits (IC) can be achieved by reuse of preexisting intellectual property (IP) cores, such as digital signal processors, microcontrollers, processors, I/O peripherals, and memory. Such IP cores are discussed in “Blocking in a System on a Chip”, by Hunt and Rowson, published in the November 1996 edition of
IEEE Spectrum
and incorporated herein by reference. Marketing of IP cores, as a way to expedite the fabrication of highly complex system chips, changes the way the cores are designed for testability. Typically, most IP cores were first designed as stand alone ICs to be used on a circuit board. With today's advanced IC fabrication technology, it is possible to migrate what was once a circuit board of plural ICs into a single IC comprising plural cores embedded therein. Thus a transition from IC to embedded IP core is a technology trend.
Many of the same testing problems currently seen in circuit boards designed with multiple ICs will be seen in ICs designed with multiple cores.
The use of IC resident testability standard, IEEE Std 1149.1, incorporated herein by reference, has proven to be effective in resolving most test problems related to testing ICs and the interconnections between ICs at the circuit board level. This standard should be effective in resolving problems related to testing cores and the interconnections between cores at the IC level as well.
FIG. 1
illustrates the architecture of IEEE Std. 1149.1 implemented in a conventional IC. The architecture includes (1) a test access port (TAP)
11
which further comprises a TAP controller and an instruction register, (2) a plurality of test data registers (boundary scan register and others), and (3) an 1149.1 test port interface which provides external I/O to the architecture via the TAP controller. These elements and their operation and function are well known and described in IEEE Std. 1149.1. The boundary scan register includes a scan cell at each input, output, control, and input/output pin of the IC.
In normal mode, the IC operates normally to internally process and externally communicate signals to other ICs via the transparent boundary scan register. In a first test mode, the functional circuitry of the IC is disabled and the boundary scan register is accessed and controlled, via TAP signal lines at
13
,
15
and
17
, to communicate external test signals between ICs to verify their interconnectivity. This external interconnect test mode is invoked by scanning an 1149.1 Extest instruction into the instruction register of the TAP
11
. In another test mode, the IC's functional circuitry may be functionally disabled but configured to be testable via scan access (from the TAP) to one or more of the test data registers. Instructions scanned into the instruction register of the TAP are used to connect the TAP up to a selected test data register(s), i.e. the boundary scan register and/or internal test data registers, so that serial test data can be input and output to the register to effectuate a given test or other type of operation. For example; when the Extest instruction is loaded into the instruction register, the TAP selects and connects up to the boundary scan register via its serial input
15
, serial output
13
, and control signals
17
. Once connected, the TAP responds to the external test port signal pins of the IC to output control to the boundary scan register to communicate test data to the boundary scan register to execute interconnect testing. Similarly, other instructions can be loaded that allow the TAP to select and connect up to other test data registers so that other types of operations such as; internal scan testing, built in self test triggering (1149.1 Runbist instruction), or IC serial bypassing (1149.1 Bypass instruction), can be performed.
While the complete 1149.1 architecture of
FIG. 1
is almost always implemented in ICs to provide the external and internal testing mentioned above, it may not be completely implemented in an IP core version of an IC. More specifically, the boundary scan register portion of the architecture may not be implemented in IP cores because competition between IP core venders is largely based on IP core performance, and the boundary scan register inherently adds a disadvantageous delay (through a switch or multiplexer) to each input, output, and control (e.g. three-state control) signal associated with the IP core's boundary. A boundary scan register that is provided as part of an IP core will herein be termed a core-provided boundary scan register. An IP core having its own core-provided boundary scan register has the same general structure as the IC of FIG.
1
.
If an IP core provider does not implement the boundary scan register due to performance considerations, and if the core itself cannot be modified by the user (i.e. a hard core), then the IP core user will have to add a TAP and boundary scan register around the IP core if the user wishes to achieve interconnect testing via boundary scan. Surrounding an IP core with a TAP and boundary scan register for the purpose of isolating the IP core and performing interconnect testing between the IP core and other IP cores is a known prior art technique and is illustrated in FIG.
2
.
Within the broken-line box of
FIG. 2
is an IP core with appropriate 1149.1 architecture, but without the boundary scan register and associated signal lines
13
,
15
and
17
of
FIG. 1. A
user-added boundary scan register
25
and TAP
23
are shown outside the broken-line box. The boundary scan register
25
is unshaded to distinguish it from the core-provided boundary scan register of FIG.
1
. The TAP
23
is provided by the user to access and control the user-provided boundary scan register
25
and is separate from the TAP
21
of the IP core. The TAP
21
differs from TAP
11
and TAP
23
because TAP
21
does not support conventional 1149.1 boundary scan instructions, namely Extest and Sample/Preload. The approach shown in
FIG. 2
disadvantageously requires adding TAP
23
to provide access to and control of the user-added boundary scan register. Also, the user must be able to select either the TAP
21
for internal testing/emulation of the IP core, or the TAP
23
for interconnect testing (via the boundary scan register) between the IP core and other IP cores or circuits residing in the IC.
It is therefore desirable to permit the user to add boundary scan to an IP core without the overhead associated with adding a separate TAP to control boundary scan.
The invention permits reuse of the IP core's TAP to access a user-added boundary scan register.
REFERENCES:
patent: 5396501 (1995-03-01), Sengoku
patent: 5544174 (1996-08-01), Abend
patent: 5627842 (1997-05-01), Brown et al.
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 5744949 (1998-04-01), Whetsel
patent: 5754410 (1998-05-01), Bardsley et al.
patent: 5862152 (1999-01-01), Handly et al.
patent: 5900753 (1999-05-01), Cote et al.
patent: 6094056 (2000-07-01), Bardsley et al.
Bassuk Lawrence J.
Brady W. James
Ton David
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