Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-02-12
2004-07-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06763487
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to integrated circuits and, more particularly, to improvements in memory circuitry associated with input, output and bi-directional terminals of integrated circuits.
BACKGROUND OF THE INVENTION
Today boundary scan design in integrated circuits (ICs) is based on an IEEE standard referred to as 1149.1. In 1149.1, flip flops and/or latches, referred to from this point forward as memories, form the boundary scan cells at the IC input, output and bi-directional pins. These boundary scan cell memories are required to be dedicated for test operation. This means that the memories cannot be used functionally by the IC when testing is not being performed. In some ICs, it is technically advantageous to be able to use the memories functionally when the IC is in normal mode, then reuse the memories for test purposes when the IC is placed in a boundary scan test mode. Reuse of memories for function and test purposes is a common practice in internal scan design of ICs. However, 1149.1 boundary scan differs from internal scan in that it requires scan access of the IC's boundary while the IC is in normal mode. Therefore the memories of the boundary scan cells must be available for scanning at all times, forcing them to be dedicated test circuits.
The reason for the aforementioned full time scan access requirement of IEEE STD 1149.1 is two-fold. First, allowing the boundary scan path to be accessed during normal IC operation provides a way to take an on-line sample of the IC's inputs and outputs during normal operation. Second, allowing the boundary scan path to be accessed during normal IC operation provides a way to preload boundary scan memories with test data prior to entering the boundary scan test mode. Of these two requirements, preloading is the most important because it allows initializing the boundary scan cells at IC output pins with safe test data prior to switching the IC into boundary scan test mode.
Sampling has not proven to be a valuable test feature, due to problems of synchronizing the sampling with normal IC operation. Due to the ineffectiveness of sampling, it may become an optional 1149.1 test feature instead of a required test feature. If sampling were made optional, it would be possible to share memories between boundary scan cells and IC functional circuitry. However, if shared memories are used in the absence of the sampling requirement, establishing safe test data in output boundary scan cells to meet the preload requirement would be difficult since sharing of the boundary scan cell memories inhibits scan access during normal IC operation.
Another requirement for 1149.1 boundary scan cells is to control output pins to a predetermined logic condition during scan operations. To achieve this, prior art output boundary scan cells utilized two memories. The first memory is used for capturing and shifting data through the cell, and the second memory is used for holding stable test data at the output pin while the first memory captures and shifts. If the sampling operation, described above, is made optional, the first memory can be shared with functional logic. However, the second memory will be required and dedicated for test to maintain stable data from the output pin while the first shared memory captures and shifts data.
A new boundary scan standard proposal currently in development, referred to as IEEE P1149.2, is based on allowing first memories (capture/shift memory) of boundary scan cells to be either shared for functional and test purposes or dedicated for test. Also, P1149.2 makes the use of second memories (output hold memory) optional. P1149.2 thus permits an output boundary cell which contains only a shared capture/shift memory. Use of such an output boundary scan cell minimizes test logic, but the IC output pin controlled by such a cell would ripple during capture and shift operations of the shared capture/shift memory. The ripple effect on output pins during capture and shift operations can cause problems during boundary test, such as corruption of the test by rippling test data at the inputs of ICs which do not themselves implement boundary scan, causing them to enter into unknown and potentially dangerous states. For example, if output ripple were to occur from the outputs of a boundary scan IC to the inputs of an non-boundary scan IC, the non-boundary scan IC could respond to the rippling inputs (on say its clock, reset and/or enable pins) to enter into an undesired state. The undesired state could damage the IC or other ICs it is connected to. Furthermore, rippling outputs prevent full control of non-boundary scan ICs during test, and therefore limit what can and cannot be tested.
Since P1149.2 allows sharing of the capture/shift memory, scanning of capture/shift memories to preload test data to optional output hold memories prior to entering boundary scan test mode is not a required feature. In P1149.2, the IC can be simply switched from functional mode into test mode, and P1149.2 assumes that the functional data stored in the shared capture/shift memories of IC output boundary cells at the time of the switch will be safe test data to initially output from the IC. This means that an IC output boundary cell which uses only a shared capture/shift memory will initially output, in test mode, the logic condition previously being output in functional mode. Since the functional outputs from an IC will be unknown at the time of the switch to test mode, unknown test data will be output.
If, for example, a short to ground exists on an output pin when the switch to test mode occurs, and a logic one is stored in the shared capture/shift memory when the switch occurs, the output buffer will attempt to drive a logic one over the ground short. If multiple outputs are shorted to themselves, to ground or to the supply voltage, and shared capture/shift memories attempt to drive out competing voltage levels when switched into test mode, the IC outputs and/or IC itself could be damaged by excessive current flow. A similar problem would exist with P1149.2 output boundary cells that use the optional output hold memory in combination with a shared capture/shift memory, since the output hold memory cannot be preloaded with safe test data. So while P1149.2 may provide a fairly safe way to enter test mode without having to scan (preload) the output cells with test data, the test mode entry method is not safe when IC output pins are subjected to being shorted to ground, supply voltage, or to other pins. Thus, neither 1149.1 or P1149.2 provides a solution to resolving voltage contention problems that can occur at IC outputs when the IC is switched from functional to test mode.
FIGS. 1 and 2
illustrate two exemplary IC functional architectures that will be used to facilitate description of the prior art and the present invention. The IC example in
FIG. 1
has an input and a 2-state output and the IC example in
FIG. 2
has an input and a 3-state output. During functional operation of the ICs, input data passes through an input buffer (IB)
11
and is stored in a functional input memory (FIM)
13
, for example, a latch. The output of the FIM is input to the IC's functional core logic (FCL)
15
. The functional core logic outputs data to be stored in a functional output memory (FOM)
17
, for example, a latch, and output from the IC via an output buffer (OB)
19
in
FIG. 1
or via a 3-state output buffer (3SOB)
21
in FIG.
2
. Data is stored in the FIM and FOM(s) by control output
23
from the functional core logic. The only difference between the two ICs is that the FCL of
FIG. 2
outputs control
25
to a FOM
27
to enable or disable the IC's 3-state output buffer. Use of FIMs and FOMs at IC inputs and outputs is beneficial in high speed IC architectures, due to the synchronizing or pipelining effect they provide for rapid IC data input and output movement. Also FIMs and FOMs can be positioned physically close to the input and output buffers, respectively, reducing input and output time dela
Bassuk Lawrence J.
Brady W. James
De'cady Albert
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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