IC with TAP, STP and lock out controlled output buffer

Details IC with TAP, STP and lock out controlled output buffer IC with TAP, STP and lock out controlled output buffer

2007-05-15

2007-05-15

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S734000

Reexamination Certificate

active

11273754

ABSTRACT:
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an output connected to a serial data output lead. A first gate has an output connected to the control input of the first buffer, a scan output enable input connected to a scan circuitry control output lead, and a lock out signal input. A second buffer has an input connected to a test data output lead, an input connected to a buffer enable output lead, and an output connected to a serial data output lead. This structure provides for selecting data outputs between the TAP and internal scan test ports.

REFERENCES:
patent: 5453992 (1995-09-01), Whetsel
patent: 5606566 (1997-02-01), Whetsel
patent: 5701308 (1997-12-01), Attaway et al.
patent: 6163864 (2000-12-01), Bhavsar et al.
patent: 6314539 (2001-11-01), Jacobson et al.
patent: 6408414 (2002-06-01), Hatada
patent: 6449755 (2002-09-01), Beausang et al.
patent: 6658614 (2003-12-01), Nagoya
patent: 6658632 (2003-12-01), Parulkar et al.
patent: 6671840 (2003-12-01), Nagoya
patent: 2005/0050414 (2005-03-01), Whetsel

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