IC with protocol selection memory coupled to serial scan path

Details IC with protocol selection memory coupled to serial scan path IC with protocol selection memory coupled to serial scan path

2006-01-13

2008-03-11

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07343537

ABSTRACT:
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded for observation and test of variable width data buses and variable width signature analysis.

REFERENCES:
patent: 4357703 (1982-11-01), Van Brunt
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4783785 (1988-11-01), Hanta
patent: 4857835 (1989-08-01), Whetsel, Jr.
patent: 4893072 (1990-01-01), Matsumoto
patent: 5054024 (1991-10-01), Whetsel
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5495487 (1996-02-01), Whetsel, Jr.
Ohletz, et al., Overhead in Scan and Self-testing Designs, International Test Conference, Sep. 1-3, 1987, pp. 460-470.
Wang, et al., Concurrent Built-In Logic Block Observer (CBILBO), IEEE International Symposium I On Circuits and Systems, May 5-7, 1986, vol. 3, pp. 1054-1057 I.
Fvan Riessen, R P, Kerkhoff, H G, Kloppenburg, A., “Design and Implementation of a Hierarchical Testable Architecture Using the Boundary Scan Standard”, Proceedings, 1stEuropean Test Conference, Paris, France, Apr. 12-14, 1989, pp. 112-118.

Affiliated with

Also associated with

Rating

IC with protocol selection memory coupled to serial scan path does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IC with protocol selection memory coupled to serial scan path, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IC with protocol selection memory coupled to serial scan path will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3973486