Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-01-10
2004-04-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S730000
Reexamination Certificate
active
06728915
ABSTRACT:
BACKGROUND OF THE INVENTION
In
FIG. 1
, a prior art example of a dedicated boundary scan path or register exists around a master circuit
102
, a slave
1
circuit
104
, and a slave
2
circuit
106
. The master circuit, such as a DSP, CPU, or micro-controller, is a circuit that controls the slaves. The slave circuits are circuits being controlled by the master, such as RAM, ROM, cache, A/D, D/A, serial communication circuits, or I/O circuits. The master and slave circuits could exist as individual intellectual property core sub-circuits inside an integrated circuit or IC, or as individual ICs assembled on a printed circuit board or multi-chip module (MCM). The scan paths
108
-
112
around each circuit are connected together serially and to a test data input (TDI)
114
, which supplies test data to the scan paths, and a test data output (TDO)
116
, which retrieves data from the scan paths.
For simplification, only a portion of the scan paths
108
-
112
of each circuit is shown. The scan paths of
FIG. 1
are designed using dedicated scan cells, indicated by capital letters (C) and (D) in circles. The word dedicated means that the cell's circuitry is used for testing purposes and is not shared for functional purposes. The scan cells are located between the internal circuitry and the input buffers
128
and output buffers
130
of the slaves and master circuit.
In
FIG. 2
, an example of a dedicated scan cell consists of multiplexer
1
(MX
1
)
202
, memory
1
(M
1
)
204
, memory
2
(M
2
)
206
, and multiplexer
1
(MX
2
)
208
. This scan cell is similar to scan cells described in IEEE standard 1149.1, so only a brief description will be provided. During operation in a functional mode, functional data passes from the functional data input (FDI)
212
to the functional data output (FDO)
214
. In a functional mode, control inputs
210
to the scan cell can: (1) cause FDI data to be loaded into M
1
via MX
1
during a capture operation; (2) scan data from TDI
216
through MX
1
and M
1
to TDO
218
during a shift operation; and (3) cause data in M
1
to be loaded into M
2
during an update operation. Neither the capture, shift, nor update operation disturbs the functional data passing between FDI and FDO. Thus the scan cell of
FIG. 2
can be accessed and pre-loaded with test data while the cell is in functional mode. The data scan cell (D) associated with the D
31
output of slave
1
104
has connections corresponding to the FDI
212
, TDI
216
, FDO
214
, and TDO
218
signal connections of the
FIG. 2
scan cell.
During a functional mode of operation of the circuit in
FIG. 1
, data is transferred from one of the slaves to the master via a 32-bit data bus (D
0
-
31
), indicated by the wired bus connections
126
. In a functional mode the scan cells are transparent, allowing functional control and data signals to pass freely through the cells. In this example, the master enables slave
1
to transfer data by the ENA
1
control signal, which is output from the master to slave
1
. Likewise the master enables slave
2
to transfer data by the ENA
2
control signal, which is output from the master to slave
2
. While only two slave circuits are shown, any number could be similarly connected to and operated by the master. Since all the scan cells of the scan paths
108
-
112
are dedicated for test, they can be scanned from TDI to TDO without disturbing the functional mode of the
FIG. 1
circuit.
As mentioned, being able to scan data into the scan paths during functional mode allows pre-loading an initial test pattern into the scan paths. The initial test pattern establishes both a data test pattern in the data scan cells (D) and a control test pattern in the control scan cells (C). By pre-loading an initial test pattern into the scan paths, the circuits can safely transition from a functioning mode to a test mode without concern over bus contention between the slave circuit's data busses. For example, the ENA
1
122
and ENA
2
124
control scan cells (C) can be pre-loaded with control data to insure that only one of the slave's D
0
-
31
data busses is enabled to drive the wired bus connection
126
. Maintaining output drive on one of the slave data busses upon entry into test mode prevents the wired data bus
126
from entering into a floating (i.e. 3-state) condition. Preventing bus
126
from floating is desirable since a floating input to input buffers
128
of master
102
could cause a high current condition.
When test mode is entered, functional operation of the master and slave circuits stop and the scan cells in the scan paths take control of the master and slave circuit's data and control signal paths. A data scan cell (D) exists on each of the 32-bit data signal paths of each circuit
102
-
106
, and a control scan cell (C) exists on each of the ENA
1
and ENA
2
control paths of each circuit
102
-
106
.
Having dedicated data and control scan cells located as shown in
FIG. 1
, enables safe test entry and easy interconnect testing of the wiring between the master and slave circuits when the scan paths are placed in test mode. During interconnect test mode, a capture, shift, and update control sequence, such as that defined in IEEE standard 1149.1, can be used to control the scan paths.
To prevent contention between slave
1
and slave
2
data outputs
126
during the capture, shift, and update control sequence, the 3-state control outputs
118
-
120
of the ENA
1
and ENA
2
control scan cells
122
-
124
do not ripple during the capture and shift part of the control input sequence. This is accomplished by having the data in M
2
of
FIG. 2
be output, via MX
2
, during the capture and shift operation. Only during the update part of the control input sequence are the outputs
118
-
120
of the control scan cells
122
-
124
allowed to change state by new data being loaded into M
2
. Similarly, the outputs from the data scan cells (D) do not ripple during capture and shift operations, but rather change state only during the update part of the control input sequence.
In
FIG. 3
, a prior art example of a shared boundary scan path exists around a master
302
and slave circuits
304
-
306
. As in
FIG. 1
, the scan paths
308
-
312
around each circuit are connected together serially and to a test data input (TDI), which supplies test data to the scan paths, and a test data output (TDO), which retrieves data from the scan paths. The scan paths of
FIG. 3
are designed using shared scan cells (C) and (D), i.e. the scan cell memory is shared for both test and functional purposes. As an aid to indicate use of shared scan cells as opposed to dedicated scan cells, the shared scan cells of FIG.
3
and subsequent figures are shown positioned outside the boundary scan paths
308
-
312
and in the functional circuits. The dedicated scan cells of
FIG. 1
were shown positioned inside the boundary scan paths
108
-
112
. Again, for simplification, only a portion of each circuit's boundary scan path is shown.
In
FIG. 4
, an example of a conventional shared scan cell consists of a multiplexer (MX)
402
and a memory (M)
404
. During a functional mode of operation, control inputs
406
form a path between FDI
408
and the data input of M
404
via MX
402
, to allow functional data to be clocked from FDI to FDO
410
. During a test mode, the control inputs
406
cause FDI data to be clocked into M via MX during a capture operation, and cause test data to be clocked from TDI
412
to TDO
414
during a shift operation. Since M
404
is used functionally, it cannot be accessed and pre-loaded with test data as can the scan cell of FIG.
2
. Thus the ability to access and pre-load test data while the master and slave circuits of
FIG. 3
operate functionally is one of the key distinctions between dedicated (
FIG. 2
) and shared (
FIG. 4
) scan cells.
In
FIG. 3
, the data scan cell associated with the D
31
output of slave
1
304
is labeled to indicate the FDI
408
, TDI
412
, FDO
410
, and TDO
414
signal connections of the
FIG. 4
scan cel
Bassuk Lawrence J.
De'cady Albert
Torres Joseph D.
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