IDDQ test solution for large asics

Details IDDQ test solution for large asics IDDQ test solution for large asics

1997-11-20

2001-04-03

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000

Reexamination Certificate

active

06212655

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to testing of integrated circuits for potential defects, and specifically to the identification of Iddq test vectors. These vectors produce minimal leakage currents in a defect-free circuit and, therefore, should reveal significant leakage currents in a defective circuit.
BACKGROUND OF THE INVENTION
While in steady-state operation, a defect-free CMOS circuit draws a minimal, but acceptable, amount of leakage current. In contrast, a defective CMOS chip produces a large quiescent current by virtue of a direct current path from the power supply to ground. The existence of such a path may lead to a reliability and performance degradation of the device. There are several methods, including current supply monitoring, for determining whether an integrated circuit is defect free.
The technique of monitoring supply current, commonly referred to as IDDQ or quiescent-current testing, has been established as an effective technique for assuring the quality and reliability of CMOS circuits. In an IDDQ test, a set of input vectors is applied to a chip in order to detect whether the circuit, in response to the stimuli, produces an unacceptably large quiescent current. Due to the size and complexity of many circuits, a small subset of all possible vectors is usually preselected for use in an IDDQ test. Simulation is one of the techniques used for preselecting a reduced set of test vectors.
In circuit simulation, using a conventional circuit simulator such as Verilog-XL or Quickhdl, a set of input vectors is applied to a model of the circuit under test. The steady-state response of each simulated circuit node is monitored and recorded. If in response to a simulated input vector, none of the simulated circuit nodes settle on a high-current state the vector is identified as a revealing test vector. This is because any quiescent current produced by an actual circuit in response to the identified test vector must be attributed to a circuit defect rather than to a high-current state. Simulated test vectors that yield high-current states are ignored, since they are not likely to distinguish an acceptable circuit from one that is defective.
As the size and complexity of CMOS circuits continue to increase, the size of the simulation results files follow suit. Also, the expense and time required to identify the subsets of test vectors using the above technique increases. Thus there is a need for a means to quickly and cheaply identify the smallest sets of test vectors that adequately test the circuits in question.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a method for selecting input vectors for testing integrated logic circuits uses a preprocessor, a simulator, and a vector identifier. The preprocessor identifies from a model of the circuit those nodes which have a greater-than-average chance of assuming a high-current state. The simulator applies a complete set of input vectors to the circuit model and records the responses of those nodes identified by the preprocessor. From the set of recorded nodal responses, the vector identifier identifies those input vectors that have produced no high-current states within the simulated circuit. These vectors are sent to a user or software application for use in testing actual circuits.


REFERENCES:
patent: 5390193 (1995-02-01), Millman et al.
patent: 5410548 (1995-04-01), Millman
patent: 5546408 (1996-08-01), Keller

Affiliated with

Also associated with

Rating

IDDQ test solution for large asics does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IDDQ test solution for large asics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IDDQ test solution for large asics will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2486097