Identification and test generation for primitive faults

Details Identification and test generation for primitive faults Identification and test generation for primitive faults

1997-04-21

2000-01-25

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060188138

ABSTRACT:
A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault. The procedure for identifying a primitive fault also produces a test for the fault. A complete algorithm is presented for identifying and testing double path delay faults. A similar procedure can be used to identify primitive faults consisting of three or more paths. Experimental results on several multi-level combinational benchmark circuits are included to demonstrate the usefulness and efficiency of the technique.

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W. Ke et al, "Delay-Verifiability of Combinational Circuits Based on Primitive Faults", Proceedings of the IEEE International Conference on Computer Design, pp. 86-90, Oct. 1994.
A. Krstic et al, "Generation of High Quality Tests for Functional Sensitizable Paths", Proceedings of 13.sup.th VLSI Test Symposium, pp. 374-379, May 1995.
U. Sparmann et al, "Fast Identification of Robust Dependent Path Delay Faults", Proceedings of the 32.sup.nd Design Automation Conference, pp. 119-125, Jun. 1995.
KT Cheng et al, "Delay Testing for Non-Robust Untestable Circuits", Proceedings of IEEE International Test Conference, pp. 954-961, Oct. 1993.

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