IC with test cells having separate data and test paths

Details IC with test cells having separate data and test paths IC with test cells having separate data and test paths

1997-03-25

2000-06-27

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060819162

ABSTRACT:
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

REFERENCES:
patent: 4833676 (1989-05-01), Koo
patent: 5241265 (1993-08-01), McDonnell et al.
patent: 5490151 (1996-02-01), Feger et al.
patent: 5495487 (1996-02-01), Whetsel, Jr.
patent: 5550843 (1996-08-01), Yee
patent: 5719876 (1998-02-01), Warren

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