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Electronic system for testing a set of multiple chips...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electronic system for testing chips having a selectable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electronic system having a chip integrated power-on reset circui

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electronic system with self-test function and simulation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Electronics testing circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded field programmable gate array for performing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded micro computer unit (MCU) for high-speed testing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded processor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded sequence checking

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded testing capability for integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Embedded testing capability for integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Emulation cache access for tag view reads

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enabling at speed application of test patterns associated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enabling multiple testing devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enabling special modes within a digital device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Encoder and method for encoding data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enhanced debug scheme for LBIST

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enhanced diagnosis with limited failure cycles

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enhanced fault coverage

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Enhanced JTAG interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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