Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-31
2002-03-26
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S726000, C702S118000, C324S1540PB, C324S765010
Reexamination Certificate
active
06363510
ABSTRACT:
RELATED CASES
The present invention, as identified by the above docket number and title, is relate to two other inventions, which are described herein with one common Detailed Description. These two related inventions are identified as Docket 550,609 entitled “A PROGRAM STORAGE DEVICE CONTAINING INSTRUCTIONS THAT ARE SPACED APART BY UNUSED BITS THAT END ON WORD BOUNDARIES AND WHICH GENERATE CHIP TESTING BIT STREAMS OF ANY LENGTH”, having U.S. Ser. No. 09/387,197; and Docket 550,611 entitled “AN ELECTRONIC SYSTEM FOR TESTING A SET OF MULTIPLE CHIPS CONCURRENTLY OR SEQUENTIALLY IN SELECTABLE SUBSETS UNDER PROGRAM CONTROL TO LIMIT CHIP POWER DISSIPATION”, having U.S. Ser. No. 09/386,945. Patent applications on all three inventions were filed concurrently in the U.S. Patent Office on Aug. 31, 1999.
BACKGROUND OF THE INVENTION
The present invention, as recited by the claims, covers an electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits. In the prior art, a related electronic system for testing chips is disclosed in U.S. Pat. No. 5,390,129. This prior art system is assigned to Unisys Corporation, who also is the assignee of the present invention.
A simplified block diagram of the prior art chip testing system is shown in FIG. 2 of patent '129. That system includes a computer 50 which is coupled via a time-shared bus 52 to a plurality of driver boards 100; and each driver board 100 is coupled to a respective burn-in board 500 which holds several integrated circuit chips that are to be tested.
In operation, the computer 50 sequentially sends each driver board 100 a separate set of test data patterns that are used to test the chips. These test data patterns are stored on each driver board in a large SRAM which is shown in FIG. 3 by reference numeral 107 and is shown in greater detail in FIG. 9 by reference numeral 145. Which particular driver board receives and stores the test data patterns at any one time is determined by an address circuit 100A that is on the driver board, as is shown in the FIG. 2 block diagram.
After the test data patterns are stored in the SRAM 145 on all of the driver boards 100, then the chips on all of the burn-in boards 500 can be tested in parallel. To do that, the test patterns are concurrently read from all of the SRAMs and sent through respective output driver modules 164, as shown in FIG. 14, to the chips on all of the burn-in boards 500.
One particular feature of the chip testing system in patent '129 is that each burn-in board includes an ID code which identifies the types of chips that are to be tested on the board. That ID code is sensed by the drive board 100 and sent to the computer 50; and in response, the test data patterns which the computer 50 sends to the driver board are tailored to the ID code that is sensed.
However, the chip testing system in patent '129 also has some major limitations which are imposed by the FIG. 2 architecture. For example, the computer 50 is the sole source of the test data patterns for all of the driver boards 100. Consequently, the speed of operation of the chip testing system is limited because the computer 50 can only send the test data patterns to a single driver board at a time over the bus 52.
Another limitation of the chip testing system in patent '129 is that each driver board 100 always tests all of the chips on a burn-in board 500 concurrently. However, each burn-in board inherently has a limit on the total amount of power which the chips on the board can dissipate. Thus, in order to keep the total power dissipation on each burn-in board 500 below a certain limit, the total number of chips on each burn-in board must be decreased as the maximum power dissipation per chip increases.
Still another limitation of the chip testing system in patent '129 is that the stored test data patterns in the large SRAM 145 on each driver board can make very inefficient use of the SRAM memory cells. FIG. 9 of patent '129 shows that each SRAM 145 receives nineteen address bits and has eight data output bits; and thus the SRAM 145 on each driver circuit has eight million memory cells. But, certain types of chips are tested by sending them sequences of serial bit streams that vary in number with time. Thus, if an SRAM 145 sends four bit streams during one time interval and sends only two bit streams during other time intervals, then half of the SRAM is wasted when the two bit streams are being sent.
Accordingly, a primary object of the chip test testing system which is disclosed herein is to address and overcome all of the above limitations.
BRIEF SUMMARY OF THE INVENTION
The present invention, as recited by the claims, covers one aspect of the disclosed chip testing system which addresses the above limitation regarding the speed of operation. In accordance with the present invention, a system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and it sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel.
Sine all the chip driver circuits which are coupled to one separate bus receive the words of the bit streams simultaneously from one pattern generator, the speed of operation is increased over the prior art. Also, since all of the pattern generators send different bit streams at the same time on separate busses, the speed of operation is further increased over the prior art.
REFERENCES:
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 5390129 (1995-02-01), Rhodes
patent: 5436912 (1995-07-01), Lustig
patent: 5666049 (1997-09-01), Yamada et al.
patent: 6219811 (2001-04-01), Gruetzner et al.
Barr Timothy Allen
Conklin Robert David
Rhodes James Vernon
Fassbender Charles J.
Moise Emmanuel L.
Rode Lise A.
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