Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-03-11
2008-03-11
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S738000, C375S224000
Reexamination Certificate
active
07343535
ABSTRACT:
Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional test controller (FTC) for mode setting and a functional test interface (FTI) for implementing the test procedures. The FTI of each tester is inserted between the SERDES of the same block and core processing logic that is also embedded within the integrated circuit. The FTCs are all interconnected via a test bus that is connected to an input/output controller (IOC) for communication between the testers and an external source, such as a personal computer. Optionally, a built-in-self-tester (BIST) state machine is connected to the test bus.
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Avago Technologies General IP Dte Ltd
Britt Cynthia
Tabone, Jr. John J.
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