Enabling at speed application of test patterns associated...

Details Enabling at speed application of test patterns associated... Enabling at speed application of test patterns associated...

2006-01-24

2006-01-24

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S025000, C714S030000

Reexamination Certificate

active

06990621

ABSTRACT:
According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester. For example, an integrated circuit might include a processor core to exchange information via input and output paths (e.g., the paths might be associated with a bus external to the integrated circuit). The integrated circuit might also include a cache structure to store test information and a sequencer to transfer the test information from the cache structure. According to some embodiments, a multiplexer receives sets of signals from (i) at least a portion of the bus and (ii) the sequencer. Moreover, the multiplexer might provide one of the received sets of signals to the processor core via the input paths.

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