Embedded sequence checking

Details Embedded sequence checking Embedded sequence checking

2006-12-19

2006-12-19

Kerveros, James C. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07152193

ABSTRACT:
A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.

REFERENCES:
patent: 4534030 (1985-08-01), Paez et al.
MIPS Technologies, “EJTAG Specification”, Document No. MD00047, Revision 2.60, Feb. 15, 2001, pp. 1-130.

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