Enhanced JTAG interface

Details Enhanced JTAG interface Enhanced JTAG interface

2007-10-16

2007-10-16

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

11024574

ABSTRACT:
An enhanced JTAG interface provides an additional clock output at any desired I/O port of a logic device during normal operation. The interface includes a boundary scan data cell associated with each I/O port that enables either input data to the I/O port in a normal mode or routes the boundary scan input data during a JTAG operation. A control cell is associated with each data cell for selectively enabling either a normal mode or a JTAG mode of the boundary scan cell. A set of JTAG instructions enable/disable JTAG operation and select JTAG functions. The boundary scan data cell is modified to incorporate a multiplexing arrangement to selectively route the JTAG clock to the I/O port when required. The control cell is modified to selectively enable/disable the routing of the JTAG clock in the boundary scan data cell.

REFERENCES:
patent: 6567943 (2003-05-01), Barnhart et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 7007099 (2006-02-01), Donati et al.

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