Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-15
2003-11-11
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000
Reexamination Certificate
active
06647525
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly to an electronics testing circuit and method.
BACKGROUND OF THE INVENTION
Electronic circuits may be tested to accomplish various functions. A circuit may be tested to determine whether there are physical defects. A circuit may also be tested to determine its response to certain inputs, a kind of testing that may be referred to as emulation. Testing is typically performed using IEEE standard 1149.1, also described as JTAG, which uses several pins on the circuit to send and receive signals during testing. Requiring pins for testing purposes may make those pins unavailable for non-testing functions. Circuits with fewer pins have fewer options to combine input and output needed for non-testing functions with support for testing and emulation under the JTAG standard.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for an improved electronics testing system. The present invention provides an electronics testing circuit and method that substantially reduce or eliminate problems associated with prior electronic testing systems.
In accordance with the present invention, an electronics testing circuit comprises a tested circuit which includes testing cells and a first transceiver coupled to the cells. The first transceiver is operable to transmit signals received from the testing cells and to receive signals transmitted for the cells. A second transceiver is operable to receive signals from the first transceiver and send signals to the first transceiver. A testing device is coupled to the second transceiver and is operable to send signals to it for the testing cells and receive signals from the testing cells.
More specifically, in accordance with one embodiment of the present invention, the tested circuit may include a modulator and a demodulator. An additional pair of modulator and demodulator may be coupled between the second transceiver and the testing device. The modulators and demodulators are operable such that the transceivers transmit and receive the signals in modulated form.
Technical advantages of the present invention include providing an electronics testing circuit. In particular, the electronics circuit may allow communications between the testing cells in the tested circuit and a testing device without using the pins of the tested circuit. Accordingly, pins on the tested circuit are not dedicated to emulation, or more broadly, testing. As a result, the number of pins available for implementing consumer functionality is increased.
REFERENCES:
patent: 5960191 (1999-09-01), Sample et al.
patent: 6349396 (2002-02-01), Akram
patent: 6349398 (2002-02-01), Resnick
patent: 6357025 (2002-03-01), Tuttle
patent: 0642083 (1995-03-01), None
patent: WO 9932893 (1999-07-01), None
Brady III W. James
Dildine R. Stephen
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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