Emulation cache access for tag view reads

Details Emulation cache access for tag view reads Emulation cache access for tag view reads

2006-06-07

2009-02-03

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S042000, C714S724000, C714S718000, C365S201000

Reexamination Certificate

active

07487421

ABSTRACT:
A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.

REFERENCES:
patent: 5640509 (1997-06-01), Balmer et al.
patent: 6966017 (2005-11-01), Evans
patent: 7017094 (2006-03-01), Correale et al.
patent: 2003/0084389 (2003-05-01), Kottapalli et al.

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