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Deterministic hardware reset for FRC machine

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Deterministic random LBIST

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Deterministic testing of edge-triggered logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for configuring input/output pads

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for creating a signature

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for JTAG test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for testing a device through resolution of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for testing a semiconductor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for testing integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device and method for testing integrated circuit dice in an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device for and method of coupling test signals to a device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device for controlling conformity of consumption of an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device for controlling pivoting elements

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Device for implementing hierarchical state charts and methods an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Device for indicating the fixability of a logic circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device for testing smart card and method of testing the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Device scan testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dft technique for avoiding contention/conflict in logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Diagnosable general purpose test registers scan chain design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Diagnosable scan chain

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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