Diagnosable general purpose test registers scan chain design

Details Diagnosable general purpose test registers scan chain design Diagnosable general purpose test registers scan chain design

2011-03-15

2011-03-15

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07908534

ABSTRACT:
A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2master-slave SRL type latch pairs; connects all the system ports of the L1latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1scan port is clocked by the A-clk and L2scan port is clocked only by the B-clk. The L1latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1latches.

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