Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-06-03
1999-11-30
Teska, Kevin J.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 38, 714 39, G05B 19045
Patent
active
059957395
ABSTRACT:
The present invention discloses apparatus implementing hierarchical state charts and including a state machine engine (SME) operative to carry out repertoires of behaviors of a system, a state chart encoder operative to replicate, in computer code form, a user-defined hierarchical state chart describing a repertoire of behaviors of the system, the encoder being operative to preserve the state chart's hierarchical structure intact in a first data structure, an event list generator operative to generate, for each individual event from among a plurality of events within the repertoire, a list of at least one transition between states of the state chart which are associated with the individual event, the event list generator being operative to preserve the list in a second data structure, and a behavior implementer operative to activate the system to carry out each of the behaviors in its repertoire.
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David Harel, Statecharts: A Visual Formalism For Complex Systems, Science of Computer Programming 8 (1987), pp. 231-274.
Emultek Ltd.
Frejd Russell W.
Teska Kevin J.
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