Diagnosable scan chain

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S819000

Reexamination Certificate

active

07007214

ABSTRACT:
A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

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James L. Shafer, et al.,Partner SRLS For Improved Shift Register Diagnostics, IEEE VLSI Test Symposium, 1992, pp. 198-201, Paper 9.3, IBM East Fiskvill Facility, Route 52, Hopewell Junction, New York 12533.

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