Device and method for testing integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

active

11023457

ABSTRACT:
The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number pattern is inputted so that a signal value in the circuit is defined by a logic simulation using the inputted pattern, as a result of which the controllability, observability and testability are calculated. A target failure minimizing the testability is selected from the list, for which target failure path-sensitization is performed using the controllability and observability of the input pattern, which pattern is corrected so as to minimize the number of inversions of signal values of the input pattern. A failure simulation for the target failure is also performed using the corrected pattern, and when a failure to be detected further exists, the failure is removed from the failure list.

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English language translation of “Fault Tolerant Computing, Maruzen Advanced Technology”, (ed) Masao Mukaidono, Maruzen, Sep. 30, 1989. pp. 124-126, 128. (Copies of the first and back covers, table of contents, part pp. 124-129 of Japanese original are attached).

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