Device scan testing

Details Device scan testing Device scan testing

1999-01-29

2001-12-04

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06327683

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuitry which enables all connections to a device, including built-in self-test capability to be included in a scan chain for scan testing, and particularly but not exclusively to a memory storage device.
BACKGROUND TO THE INVENTION
Scan testing is a well established technique for checking the interconnections of integrated circuits, as well as for checking the functionality and performance of logic circuits. IEEE Standard 1149.1-1990 defines circuitry for scan testing.
A simple scan test is intended to check integrity of connections in an integrated circuit. This is achieved by feeding a scan chain of test information through the connections and ensuring that the correct information is scanned out.
However, certain blocks within integrated circuit devices do not lend themselves to full scan testing. For instance a memory device such as a RAM has data, address, and control inputs, and data output. However the data output is not directly linked to the data, address and control inputs. Thus in a scan test such a memory device is normally provided with circuitry such that the data input to the memory device can be bypassed directly to its data output. In this way the data input and output connections of the memory device can be scan tested, but there is no means for scan testing the control and address inputs of the memory device. The data input to the memory device will have the same width as the data output and therefore can be readily fed directly onto its memory data output in a scan test.
In such arrangements, the memory device itself is not tested during a scan test, but is tested in a separate built-in self-test (BIST). For this purpose a BIST controller is usually provided which generates test signals for the memory device on the data input, address and control signal lines, and checks that the correct data outputs are generated by the memory device. Specifically the BIST controller may write into the memory device particular bits of test patterns, and then read the test patterns to ensure that the test patterns read are those as written.
Thus there is a deficiency in the testing of integrated circuits including such memory devices, in that the although the memory device itself can be properly tested using a built in self-test, and the data input and data output connections can be tested using a scan test, there is no means for specifically testing the integrity of the connections of the control and address signal lines.
This deficiency in applying scan testing to integrated circuits is associated not only with addressed memory devices but also is associated generally with devices having a number of inputs greater than the number of outputs and in which there is no direct correlation between the inputs and the outputs. Such other devices, may include, for example a FIFO queue, or a stack that does not take an address but instead has an internal state to cope with addressing.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide circuitry which enables a device having a greater number of inputs than outputs, such as a device in an integrated circuit having built-in self-test capabilities, to be scan tested to check for the integrity of the connections of all signal lines.
According to the present invention there is therefore provided circuitry for scan testing a device having a plurality of inputs and at least one output, the number of inputs being greater than the number of outputs, comprising an exclusive-OR gate for receiving the plurality of inputs and for generating an exclusive-OR output, a multiplexer for receiving the at least one data output and the exclusive-OR output and selectively outputting one of such as a data output, wherein responsive to a scan test signal the multiplexer outputs the exclusive-OR output as the data output in a scan chain.
An additional problem arises in that the device under test may include a clocked element. In the scan test mode where the device is bypassed, such clocked element is thus removed from the scan path. If there is a combinatorial path from the output of a device under test to the input of the next level up of the circuit design hierarchy, then this could create a combinatorial loop during bypass mode that has the potential to oscillate and is detrimental to test coverage.
Therefore the invention also preferably provides circuitry in which the device includes at least one clocked element, and further comprising a scan latch for receiving as a data input the exclusive-OR output and providing as a data output a clocked exclusive-OR output to the multiplexer.
The invention also provides a method of scan testing a device having a plurality of inputs and at least one output, the number of inputs being greater than the number of outputs, comprising exclusive-ORing the inputs to generate an exclusive-OR output, selectively outputting one of the at least one output and the exclusive-OR output, wherein the exclusive-OR output is output responsive to a scan test signal.


REFERENCES:
patent: 5258985 (1993-11-01), Spence et al.
patent: 5299136 (1994-03-01), Babakanian et al.
patent: 5428622 (1995-06-01), Kuban et al.
patent: 5642362 (1997-06-01), Savir
patent: 0 489 394 A2 (1992-06-01), None
patent: 03185696 (1991-08-01), None
patent: 93/18457 (1993-09-01), None

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