Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-22
2006-08-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C702S117000, C365S201000
Reexamination Certificate
active
07096397
ABSTRACT:
A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine whether the device is free of structural defects.
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Galivanche Rajesh
Kundu Sandip
Sengupta Sanjay
De'cady Albert
Intel Corporation
Kerveros James C.
Schwegman Lundberg Woessner & Kluth P.A.
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