Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-11
2005-10-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06954886
ABSTRACT:
A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.
REFERENCES:
patent: 3701972 (1972-10-01), Berkeley et al.
patent: 4325120 (1982-04-01), Colley et al.
patent: 5155856 (1992-10-01), Bock et al.
patent: 5163155 (1992-11-01), Omiya
patent: 5260950 (1993-11-01), Simpson et al.
patent: 5758058 (1998-05-01), Milburn
patent: 5862373 (1999-01-01), Pathikonda et al.
patent: 5935266 (1999-08-01), Thurnhofer et al.
patent: 6061599 (2000-05-01), Rhodehamel et al.
patent: 6114887 (2000-09-01), Pathikonda et al.
patent: 6125463 (2000-09-01), Macchi
patent: 6357024 (2002-03-01), Dutton et al.
patent: 6393582 (2002-05-01), Klecka et al.
patent: 6615366 (2003-09-01), Grochowski et al.
patent: 6625749 (2003-09-01), Quach
patent: 6625756 (2003-09-01), Grochowski et al.
patent: 6640313 (2003-10-01), Quach
patent: 6708304 (2004-03-01), Tsukimori et al.
Joel M. Tendler, Steve Dodson, Steve Fields, Hung Le, Balaram Sinharoy, IBM Server Group, IBM eserver, POWER4 System Microarchitecture, Technical White Paper, Oct. 2001, pp. 1-33.
David J.C. Johnson, Fort Collins Microprocessor Lab, HP's Mako Processor, Oct. 16, 2001, 16 pgs.
Sun Microelectronics, MicroSPARC-llep™, Introduction to JTAG Boundary Scan, White Paper Jan. 1997 (10 pgs).
Nguyen Hang T.
Tu Steven J.
Blakely Sokoloff Taylor and Zafman
De'cady Albert
Trimmings John P.
LandOfFree
Deterministic hardware reset for FRC machine does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Deterministic hardware reset for FRC machine, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Deterministic hardware reset for FRC machine will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3460138