Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-30
2001-02-06
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S733000, C365S200000, C365S201000
Reexamination Certificate
active
06185709
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to testing and repairing of electronic circuits such as logic circuits, memory circuits and combinations thereof including a memory embedded in a logic chip. Specifically, a device is provided which uses Built-In Self Test (BIST) circuitry to detect failed memory cells in a memory, and to indicate whether or not the memory can be repaired by substituting redundant rows and/or columns for defective rows and columns of the memory array. Significant advantages in electronic circuitry are realized when random access memories are embedded with logic on the same integrated circuit chip. Significant improvement in circuit performance, while effectively utilizing chip area, occurs because of the improved communication between the logic and embedded memory. In stand alone memory circuits, 16- or 32-bit input/outputs are provided having dedicated input/output pins on the memory chip which communicate off chip over a data bus. The bus overhead necessary in order to read and write to the memory, requiring numerous bus cycles to transfer data into and out of the memory, reduces the efficiency of the memory. Combining the logic circuitry on the same circuit chip permits direct connection to the input/output lines of the memory avoiding the bus overhead incurred in communication between chips.
Embedding memory devices such as static random access memories (SRAMs) or dynamic random access memories (DRAMs) having wider outputs, for instance, memories which have 128, or 256 bit outputs which are directly connected to the logic without a bus interface is especially advantageous.
The combination of memory with logic on the same chip, particularly where DRAMs are used for the memory device, produces significant manufacturing problems. For instance, the DRAM cells are sensitive to minor defects that the more durable logic will withstand. The logic may require extra wiring layers to allow tightly packed logic cells to be interconnected. The wiring necessary for the logic may, however, impair transmitted signal margins, and otherwise decrease chip yield. An additional serious consequence is the effect of testability of a chip having the embedded memory. On-board Built-In Self Test (BIST) circuitry is provided to produce a set of complex data patterns, address sequencing, and control signals to check the logic circuitry and connected memory elements. The BIST circuitry includes logic circuitry which is used to identify failed memory cells, and to allocate replacement memory cells for the failed cells. In an embedded DRAM the results of testing word lines of memory cells, as well as column lines of memory cells may be provided to the allocation logic circuit to identify failed memory cells. Faulty word line addresses are stored in a wordline register, and redundant word line memory cells in the DRAM are assigned to replace the failed wordlines by the allocation logic. The fixability of the DRAM macro, i.e., the ability to replace all defective memory cells with redundant memory cells, may be determined from an overflow bit in the register storing the faulty word line addresses. If there is an overflow bit, indicating that more word line memory elements have failed than can be replaced by redundant memory word line elements, the inability to fix the embedded DRAM is easily determined by a connected tester which monitors the overflow bit.
In some memory designs, redundant columns of memory elements are also provided to replace defective columns. As in the case of word line replacement, a second register is provided which produces an overflow bit, indicating that the number of redundant columns available for replacement have been exhausted. By ORing the overflow bits for each of the word line address registers and column line address registers, an indication of memory fixability is available to a connected tester.
Embedded memories which are organized as 128 or 256 bits wide where each bit represents a data slice derived from a memory array, do not utilize column redundancy, as it would require a large number of redundant columns increasing chip area overhead. These embedded memories provide redundant word line memory cells, along with redundant data slice arrays. Each of the memory output data bits, therefore, do not have a logical address to permit the use of the Failed Address Registers to identify the fixability of a memory. Thus, the tester does not have a way of determining whether there are more memory cell faults than there are redundant replacement cells which can be assigned to replace failed memory cells. Thus, a connected tester must download significant amounts of data from the allocation logic circuit in order to determine whether the embedded DRAM macro is fixable.
The present invention relates to an on board circuit for compressing the data output from the allocation logic to determine whether or not sufficient redundant memory elements are available to render the embedded DRAM macro fixable.
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to provide an on-chip testing device which produces a bit indicating the repairability of a logic circuit.
It is a more specific object of this invention to provide a single bit output to a connected tester to indicate if an embedded memory of a logic circuit is not repairable.
The invention provides a device for testing the fixability of a logic circuit which is tested using a specific test pattern. The test pattern provides a known stimulus to the logic circuit, and a response thereto is recorded in a register. The register comprises a plurality of stages, forming a failed data bit register. Multiplexer circuits are provided between each stage, permitting failed data bits recovered from the tested logic circuit to be stored as serial data within the register.
The contents of the register are shifted out at a convenient time, by circulating the contents of the bit register whereby the failed data bits are produced from the last stage indicating the number of failures in the tested logic circuit.
The invention in accordance with a preferred embodiment is provided in a logic circuit having an embedded memory. A Built-In Self Test (BIST) circuit generates data for testing the embedded memory, and an allocation logic circuit connected to the memory and to the test circuit identifies each bit output line of the memory which has failed or passed with a logical “1” or “0”. An level sensitive scannable register (LSSD) includes a plurality of serially connected stages. Each output bit from the allocation logic circuit is connected through a first input of a multiplex (MUX) circuit to one of the stages. The second input of the multiplex circuit is connected to the output of the preceding stage of the shift register. The last stage of the shift register, which receives the highest order bit from the allocation circuit, is connected to the multiplex circuit of the first stage which receives the lowest order bit from the allocation logic circuit.
At the end of a test cycle initiated by the BIST circuit, a Clock Cycle Counter is enabled, generating a series of clock pulses for enabling the multiplex circuit. Enablement of the multiplex circuits result in cycling of the data from the allocation logic circuit through the plurality of stages, and thence back to the first stage. A fail counter counts the number of times Failed Data-Bits are produced by the last of the stages, thus providing an indication of the number of memory elements which have failed. The fail counter produces a fixability flag when the number of fail counts exceeds the number of redundant circuits indicating the memory is not repairable. A connected tester examines the contents of the fail counter to establish whether or not the logic circuit having the embedded memory is repairable.
REFERENCES:
patent: 4000460 (1976-12-01), Kadakia et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4460999 (1984-07-01), Schmidt
patent: 4586178 (1986-04-01), Bosse
patent: 4627053 (1986-12-01), Yamaki et al.
patent: 4639915 (1987-01-
Dreibelbis Jeffrey Harris
Kho Rex Ngo
Noel Leo Armand
Cady Albert De
International Business Machines - Corporation
Lamarre Guy
Pollock, Vande Sande & Amernick RLLP
Schnurmann H. Daniel
LandOfFree
Device for indicating the fixability of a logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for indicating the fixability of a logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for indicating the fixability of a logic circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2576155