Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-22
2001-07-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010
Reexamination Certificate
active
06263464
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to conformance testing apparatus for testing electronic component consumption in a testing machine.
The invention is particularly advantageously applicable to the field of characterization or production testing of combined (analog/digital) very large scale integration (VLSI) CMOS components, and more particularly components operating under high current conditions such as microcontrollers or microprocessors.
BACKGROUND OF THE INVENTION
Generally, a machine for testing electronic components is essentially made up of three elements:
A computer which is the workstation enabling an operator to use suitable software for preparing the tests to be performed on the electronic components, e.g. components coming off a production line, so as to check that they operate properly. The test program is organized in a succession of test rows which must be executed in application of a given sequence, each test row indicating the logic signals or test signals to be applied simultaneously to certain pins of the components.
An electronic rack connected to the computer via a central processing unit, which rack includes a certain number of members serving firstly, such as a test sequencer, to generate said logic signals in application of the test sequence prepared by the operator, and secondly to compare the logic signals delivered at other pins by the components, in response to the test signals, with pre-defined responses to be expected if the components operate properly.
A work head in which the electronic components to be tested are disposed, the work head being provided with an electronic pin serving to put into analog form the test logic signals received from the electronic rack, depending on the technology and on the logic used by the components, and, conversely, to put into logic form the analog responses from the components prior to transmitting them to the rack for comparison purposes.
Furthermore, the electronic rack includes a DC power supply subassembly serving to apply to the components under test the bias voltages that are necessary for them to operate. This subassembly includes as many electrical power supply circuits per component as is necessary to power the component. Depending on the type of component to be tested, there exist various electrical power supplies which differ in that they have different maximum values for the bias current taken: cards are known having current values that are very low (up to 0.5 A), low (up to 4 A), high (up to 30 A), etc.
The various circuits of the power supply subassembly not only serve to power the components under test, they also serve to deliver a measurement of the current taken by each component. It is very important for a manufacturers to be able to subject the electronic components manufactured by them to consumption conformance testing, in particular since currents taken tend to become increasingly high. For this purpose, the electrical power supply circuits of testing machines are equipped with current-measuring means in known manner.
The command to perform current measurement may come from the central processing unit itself at moments in the test sequence that are defined initially by the operator at the same time as the test program is being prepared. It is also possible for the command to come from a current measurement sequence have a succession of measurement rows, each of which corresponds to a test row of the test sequence, and contains a measurement flag representative of a command to perform or not to perform a current measurement. Said measurement sequence constitutes a kind of supplement to the test sequence. Naturally, the measurement sequence flags are predefined by the operator, prior to execution of the tests proper.
Currently, the value of the current as measured, in application of a command coming either from the central processing unit of the electronic rack, or from the pre-established measurement sequence, is compared with at least one reference value by said central processing unit itself. That suffers from a certain number of drawbacks. Firstly, the running of the test sequence is interrupted each time the current is measured, in order to be informed of the result of the comparison so as to decide whether to stop the tests or to continue them. If the specified number of current measurements is large, a considerable amount of time is wasted during the tests. Furthermore, after each interruption in the test sequence for the purpose of measuring the current, the test sequence starts again from the beginning for reasons of initialization, which lengthens the test time even further. Unfortunately, today, test time is an increasingly large factor in the cost of electronic components.
SUMMARY OF THE INVENTION
Therefore, the technical problem to be solved by the present invention is to provide conformance testing apparatus for testing the consumption of an electronic component in a testing machine, the apparatus including:
at least one electrical power supply circuit for powering the component, which circuit includes current-measuring means for measuring the current taken by said electronic component;
a test sequencer suitable for executing a sequence of test rows to be applied to the component; and
a current measurement sequencer suitable for executing a sequence of measurement rows, each of which corresponds to a test row, and contains a measurement flag defined prior to execution of the test sequence and representative of a command to perform or not to perform a current measurement;
such an apparatus making it possible to avoid wasting time when running tests, such time wasting being induced in currently used testing machines by measuring the current taken and by comparing the results obtained with one or more reference values.
According to the invention, the solution to the technical problem posed consists in that said measurement sequencer includes a multiple acquisition memory having a plurality of acquisition rows, each of which corresponds to a measurement row of the measurement sequence whose measurement flag is positive, said memory including for each acquisition row:
at least one limit value zone in which a limit value for the current taken by the electronic component is written prior to execution of the test sequence; and
at least one conformance zone in which, for each measurement, a conformance flag is written representative of the result of a comparison performed in a register associated with said memory between the current as measured and said limit value.
Thus, in the apparatus of the invention the comparison between the current as measured and the limit value is no longer performed by the central processing unit, but rather it is performed in the multiple acquisition memory, in a register provided for this purpose, the result of the comparison, i.e. said conformance flag, being written in the memory measurement after measurement, without there being any interruption in the test sequence, and therefore without the sequence starting again from the beginning after each measurement. Once the series of tests is finished, the operator can, by reading back row-by-row the conformance zones, either note that all of the current measurements conform to expectations, or identify that moment in the test sequence at which an anomaly in the consumption of the component occurred, thereby possibly enabling the operator to determine the cause of the anomaly or to evaluate the importance thereof.
When it is merely necessary for the operator to have access to the overall result of the measurements of the current consumption of the component under test, the invention provides that said multiple acquisition memory further includes a global status row including a global conformance zone corresponding to said conformance zone, and in which a global conformance flag is written after the test sequence has been executed, the global conformance flag being positive if all of the conformance flags are positive, or negative if at least one conformance flag is negative.
In a particular e
Iafrate Gilles
Mallet Jean-Pascal
Petit Roland
De'cady Albert
Frishauf, Holtz Goodman, Langer & Chick, P.C.
Lamarre Guy
Schlumberger Systemes
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