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Automatic test equipment using sigma delta modulation to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatic test pattern generation for functional register...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatic test system with synchronized instruments

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatic testing for programmable networks of control signals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatic testing of microprocessor bus integrity

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatic testing of microprocessor bus integrity

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automatically determining test patterns for a netlist having mul

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Automaton synchronization during system verification

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Autonomic bus reconfiguration for fault conditions

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Autonomous self-monitoring and corrective operation of an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Avoiding race conditions at clock domain crossings in an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bandwidth matching for scan architectures in an integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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BDX data in stable states

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bidirectional horizontal scan circuit with sub-sampling and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Binary time-frame expansion of sequential systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bist architecture for detecting path-delay faults in a sequentia

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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BIST circuit for LSI memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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BIST memory test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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BIST scan path parts with test generator and compactor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Bit synchronizers and methods of synchronizing and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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