BIST memory test system

Details BIST memory test system BIST memory test system

1997-12-30

2001-01-30

De Cady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

06182257

ABSTRACT:

This invention relates generally to apparatus method for testing and repairing semiconductor memories and more specifically, to a built-in self test and repair system.
BACKGROUND OF THE INVENTION
Built-in self test (BIST) systems usually operate under fixed test conditions; i.e. fixed temperature and fixed voltages. This limits the range of possible scenarios which may be tested and not all scenarios faced by a device once it is in full production usage may be tested. Specifically, data storage integrity in dynamic random access memories (DRAM) can be compromised by cell leakage caused by a variety of reasons including alpha particles, hot electrons, and substrate current. Memory cells have certain operation margins which, if exceeded, will cause the cell to lose data stored therein. As a result, it is important to test a device under the worst-case scenarios in order to determine the cell's retention capabilities.
A supply voltage fluctuation test or voltage bump test is a standard test performed on standard DRAMs which is capable of testing operating margins of these cells, using an external tester. However, embedded memories cannot use standard memory testers to perform this and other tests due to the multitude of other functions contained in the integrated circuit. As a result, BIST systems provide a practical solution to testing embedded memories. BIST systems, however, usually operate at nominal temperature and voltage levels. As a result, the extreme conditions tested by the bump test are not covered. Our production testing the operating conditions are usually extended well beyond device ratings to ensure there is adequate operating margin.
Further, in standard DRAM and SDRAM applications, external testers perform a variety of tests including the voltage bump test to verify the memory cells' data retention capabilities. Under normal operations, the DRAM cell plate is held at a DC voltage, typically VCC/2. During the cell plate voltage bump test, two different voltage values are used, for example VCC/2−&Dgr;V and VCC/2+&Dgr;V. During the bump test, bits are written with one value of the cell plate voltage and read back with the other value. When the value of the cell plate is higher when writing than reading, the operation margin on stored ‘1’s is tested. When the value of the cell plate is lower when writing than reading, the operation margin on stored ‘0’s is tested.
Referring to FIG.
1
(
a
), the concept of the voltage bump test is illustrated. A typical DRAM memory cell, word line WL and bit line BL structure is shown. Under nominal operating conditions, the cell plate voltage VCP=VCC/2, the bit line BL is precharged to VCC/2, the word line receives a voltage VPP for reading or writing the data stored in the memory C
cell
. The charge delivered to the bit line BL is given by the formula:
Q=
(
C
cell
/(
C
cell
+CBL
))(
V
cell
−½
VCC
)
CBL
where V
cell
=VSS (‘0’) or VCC (‘1’)
When the voltage bump test is performed, a ±&Dgr;V bump step is applied to VCP before reading. The charge delivered to the bit line is now given by:
Q
=(
C
cell
/(
C
cell
+CBL
))(
V
cell
−½
VCC±&Dgr;V
)
CBL
Based on whether &Dgr;V is a positive bump or a negative bump, the charge delivered to the bit line will benefit either a stored ‘0’ or ‘1’. FIGS.
1
(
b
),
1
(
c
) and
1
(
d
) illustrate the voltage versus capacitance charge distributions for the three cases: nominal, &Dgr;V positive and &Dgr;V negative, respectively. Q
0
represents the charge for a stored ‘0’ and Q
1
represents the charge for a stored ‘1’. As can be seen, when &Dgr;V is positive, a stored ‘1’ provides more charge to the bit line and therefore has a higher margin than a stored ‘0’ which provides less charge to the bit line. Conversely, when &Dgr;V is negative, the stored ‘0’ has better retention capabilities than a stored ‘1’. By performing these tests, the margin on each cell for storing a ‘0’ or a ‘1’ can be verified. A voltage bump test circuit is described in U.S. Pat. No. 5,051,995.
Secondly, embedded memories usually employ a BIST system to perform the testing of the memory. The main concept of BIST is to move most of the test functionality into the silicon of the device being tested. Embedded memories require this type of testing since they do not have any external access pads or other means to connect to the external testers for testing. As a result, test systems integrated directly into the embedded memory device. U.S. Pat. No. 5,173,906 entitled “BUILT-IN SELF TEST FOR INTEGRATED CIRCUITS” illustrates such a system for an embedded SRAM macro. This system includes an input data pattern generator for generating predetermined data to be applied to the data inputs of the memory, an address counter for applying test address signals to the address inputs of the memory, an expected data pattern generator, which may be the same as the input data pattern generator, for generating expected data, a comparison circuit for comparing the expected data and the resulting data. The system is controlled by a state machine during the test sequence. The test patterns available are unique address ripple word (UARW), unique address ripple bit (UARB), checkerboard, (CHKBD), word line strip (WLS), blanket (BL) and programmable (PG). Since this BIST is designed for embedded SRAM's however, there is no provision for a voltage bump test. This system, however, does not perform a volt bump test on embedded memories, neither does it provide a facility for repairing defective memory. Recently embedded DRAMs have become widely used. Thus, here exists a need for a system that is capable of providing a built in self test along with an automatic repair of defective memory.
SUMMARY OF THE INVENTION
This invention seeks to provide a BIST system for an embedded dynamic random access memory, integrated in a single semiconductor device, including a provision for performing a voltage bump test of the embedded memory and using the test results to repair faulty memory locations.
According to an embodiment of the present invention, a semiconductor device capable of performing self test comprises: an embedded dynamic random access memory array for storing data, a built-in self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to the cell plate of the memory according to predetermined test requirements.
The memory further including redundancy circuitry for replacing faulty elements with redundant elements using the results from a test sequence.
An advantage of the present invention is that the data retention abilities of an embedded dynamic random access memory can be tested quickly and efficiently. An additional advantage of the present invention is that its additional test capabilities occupy minimal silicon area in addition to the existing BIST circuitry area. A further advantage of the present invention is the ability to detect errors and subsequently correct them without external interference in the form of standard redundancy replacement techniques.


REFERENCES:
patent: 5051995 (1991-09-01), Tobita
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5471482 (1995-11-01), Byers et al.
patent: 5481551 (1996-01-01), Nakano et al.
patent: 5535164 (1996-07-01), Adams et al.
patent: 5557619 (1996-09-01), Rapoport
patent: 5568437 (1996-10-01), Jamal
patent: 5764878 (1998-06-01), Kablanian et al.
patent: 5784323 (1998-07-01), Adams et al.
patent: 5987632 (1999-11-01), Irrinki et al.
Rajsuman et al. Testing Embedded Cores, IEEE, pg. 81 to 85, Jun. 1997.
Takeshima et al., Voltage Limiters for DRAM's with Substrate-Plate-Electrode Memory Cells, Feb. 1988.

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