Bist architecture for detecting path-delay faults in a sequentia

Details Bist architecture for detecting path-delay faults in a sequentia Bist architecture for detecting path-delay faults in a sequentia

1998-02-12

2000-11-14

Sheikh, Ayaz R.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714726, 714729, 714722, 714733, 714727, 714724, 714734, 375 221, 375 225, 39518301, 39518307, G01R 3128

Patent

active

061484253

ABSTRACT:
A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

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