Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-31
2006-10-31
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
07131043
ABSTRACT:
Techniques are provided for testing routing resources that route control signals on programmable integrated circuits (ICs). Control signals (such as clock signals) are routed through a logic gate to a test register. Values of the control signals are stored in the test register, transmitted outside the IC, and then compared to expected values to identify defects in the programmable interconnections. An enable circuit couples the control signals to functional registers on the programmable IC during user mode. The enable circuit decouples the control signals from the functional registers so that the control signals do not interfere with tests of the functional registers during test mode. During the test procedures, the control signals are treated as data signals and are not used to control other registers on the IC.
REFERENCES:
patent: 5260947 (1993-11-01), Posse
patent: 5301156 (1994-04-01), Talley
patent: 5477549 (1995-12-01), Kamagata et al.
patent: 5732246 (1998-03-01), Gould et al.
patent: 6615377 (2003-09-01), da Cruz et al.
patent: 6671848 (2003-12-01), Mulig et al.
Altera Corporation
Ton David
Townsend and Townsend / and Crew LLP
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