BIST scan path parts with test generator and compactor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

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07747919

ABSTRACT:
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator102, compactor106, and controller110remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path502, to insert scan paths A506, B508and C510, and the insertion of an adaptor circuit504in the control path114between controller110and scan path502.

REFERENCES:
patent: 5701308 (1997-12-01), Attaway et al.
patent: 5831992 (1998-11-01), Wu
“Minimized power consumption for scan-based BIST” by Gerstendorfer This paper appears in: Test Conference, 1999. Proceedings. International Publication Date: 1999 on pp. 77-84 ISBN: 0-7803-5753-1INSPEC Accession No. 6536352.
“Two techniques for minimizing power dissipation in scan circuitsduring test application” by Chakravarty This paper appears in: Test Symposium, 1994., Proceedings of the Third Asian Publication Date: Nov. 15-17, 1994 on pp. 324-329 ISBN: 0-8186-6690-0 INSPEC Accession No. 4868998.
“Core test connectivity, communication, and control” by Whetsel This paper appears in: Test Conference, 1998. Proceedings., International Publication Date: Oct. 18-23, 1998 On pp. 303-312 ISSN: 1089-3539 ISBN: 0-7803-5093-6 INSPEC Accession No. 6251460.

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