Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-03-01
2011-03-01
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000
Reexamination Certificate
active
07900109
ABSTRACT:
A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.
REFERENCES:
patent: 6430727 (2002-08-01), Warren
patent: 6675284 (2004-01-01), Warren
patent: 7159159 (2007-01-01), Sunter
Swoboda, Gary L., Compact JTAG (cJTAG), Revision 0.9, Nov. 20, 2005.
Bassuk Lawrence J.
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tu Christine T
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