Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-11
2006-07-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S050000, C714S056000, C714S030000
Reexamination Certificate
active
07076711
ABSTRACT:
Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the data bus to verify integrity of the data bus. Further bus verification may be provided by an address capture mode where address bus contents are reflected onto the data bus. A microprocessor may control diagnostic mode operation.
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Amin Hitesh
Bennett Marc Alan
Foster Philip Edward
Goody Steven Harold
Alphonse Fritz
Cisco Technology Inc.
De'cady Albert
Kaplan Cindy
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