Avoiding race conditions at clock domain crossings in an...

Details Avoiding race conditions at clock domain crossings in an... Avoiding race conditions at clock domain crossings in an...

2011-08-09

2011-08-09

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07996739

ABSTRACT:
A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.

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