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Method and apparatus for high speed IC test interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for high update rate integrated circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for high-speed interconnect testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for holding failing information of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for implementing enhanced LBIST...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for implementing multiple remote...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for improving fault test coverage for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for improving stuck-at fault detection...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for improving testability of I/O...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for improving timing accuracy of a semicond

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for improving transition fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for integrated flip-flop to support two...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for isolating faulty semiconductor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for limited access circuit test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for limiting power dissipation in test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for locating critical speed paths in integr

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for logic testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for looping back a current state to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for low overhead circuit scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for low-pin-count scan compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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