Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-09
2001-02-06
DeCady, Albert (Department: 2785)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06185713
ABSTRACT:
TECHNICAL FIELD
This application pertains to a bus holder cell for increasing the detection of “stuck-at” faults in automated fault testing of large scale integrated circuits.
BACKGROUND
Processes for automated fault testing of large scale integrated circuits commonly employ a “stuck-at fault” model to emulate possible physical defects that may occur during fabrication of the integrated circuit under test. Such models represent stuck-at defects as nodes or pins within the circuit that are continually held (i.e. “stuck”) at a single logic level, being either a one or zero. The objective is to increase single stuck-at fault coverage in large scale digital integrated circuits containing tri-statable multiplexers or other internal tri-state bus structures. Most commercially available fault grading tools adhere to Mil-Std-883D, Method 5012.1 to determine stuck-at fault coverage. In this process, each pin of each gate-leveI component within the integrated circuit under test is individually subjected to a single stuck-at fault condition. A complete set of test vectors is applied to the integrated circuit under test and the simulation results so obtained are compared with the simulation results of an identical “good” circuit (i.e. with no injected faults). If, for any one of the test vectors, the output of the faulted circuit exhibits a “hard” difference (i.e. “1” expected but “0” detected, or vice versa) from the output of the good circuit, then the stuck-at fault condition is detected.
Problems arise in the detection of stuck-at fault conditions in tri-state circuits. For example,
FIG. 1
shows three tri-state devices
10
,
12
,
14
sharing a common bus
16
. Suppose that a stuck-at fault condition exists at the ENB
1
enable pin of device
10
. This results in transfer, by device
10
, of the value at the INP
1
input pin to bus
16
. Now suppose that device
12
is enabled so as to transfer the value at the INP
2
input pin of device
12
to bus
16
. If the INP
2
value is the same as the INP
1
value, then that value is passed to the output without detection of the stuck-at fault condition at the ENB
1
pin of device
10
. If the INP
2
value is opposite to the INP
1
value, then an “X” (unknown) value is passed to the output and a “possibly detected fault” condition is noted. Because the specific condition responsible for the fault is unclear, Mil-Std-883D, Method 5012.1 does not permit the aforementioned fault to be included in the final count of detected faults. Consequently, lower test coverage is achieved.
Designers attempt to circumvent the foregoing problem by accepting reduced test coverages; or, by using non-tristatable gates. However, the latter approach tends to increase circuit size and often adversely affects speed. Another approach is to use a storage element such as bus repeater
18
to maintain a saturated logic value on the bus when all active drivers have been tristated.
Bus repeater
18
is used to identify the fault by initially charging the bus with a logic “0” or “1”. Then, all of the inputs to the tri-state devices connected to the bus are driven to the opposite value, without enabling any of those devices. The logic level on the bus is then sensed, again without enabling any of the tri-state devices. In a “good” circuit, the logic level is the same as before, namely that with which bus repeater
18
initially charged the bus. In a “bad” circuit, (i.e. a circuit in which the output enable pins of any one or more of the tri-state devices is stuck in the enabled condition) the logic level is opposite to the value with which bus repeater
18
initially charged the bus.
However, bus repeaters present additional problems. A bus repeater, being a form of non-gated flip flop, is easily strong enough to overdrive the output and change the state of the bus. In the steady state, the bus repeater maintains the state weakly, even when the original driver tristates. This is adequate for maintaining a low current state (e.g. for IDDQ testing) but presents problems in the presence of noise.
Assume that a net in the bus of interest has been driven to a high state and then the driver tristates. In this context, a “net” is equivalent to a wire segment which makes an electrical connection between a cell's input and output pins. A stuck-at fault on either the input pin or the output pin of that cell is equivalent to a single “net fault” for the cell as a whole. In other words, the minimum drive bus repeater is maintaining a logic “1” on the net, when an adjacent net (or the substrate) having significant capacitance to the tristated net switches, causing a noise glitch on the net. The bus repeater resists the noise transient to some degree. But, if the noise transient is strong enough, the bus repeater may switch to the opposite state. The bus repeater is now maintaining the incorrect state on the bus—but it is a legitimate saturated logic state (e.g. acceptable for IDDQ testing). The problem is that the “exposure time” to such noise transients is 100% of the time, because the bus repeater operates continuously; it does not “hard latch” a state based on a clock pulse window. Thus, although bus repeaters may be useful for ensuring low current states on tristated buses for IDDQ testing, they can not be relied upon for maintaining logic values in the presence of noise or crosstalk. The present invention addresses these problems.
SUMMARY OF INVENTION
In accordance with the preferred embodiment, the invention provides a bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive any logic value applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1. The bus holder's bus driving capability is less than that of any of the tri-state devices.
In one embodiment, the logic circuitry includes a first nand gate having a first inverted input coupled to the bidirectional port. A first input of a second nand gate is coupled to the first nand gate's output. The second nand gate's output is coupled to the bidirectional port. A first inverter is coupled between the first test port and a second input of the first nand gate. A second inverter is coupled between the second test port and a first input of a third nand gate. A second input of the third nand gate is coupled to the first test port and the third nand gate's output is coupled to a second input of the second nand gate.
In an alternate embodiment, the logic circuitry includes a multiplexer having a first input port coupled to a bidirectional port, a second input port coupled to the second test port, a selection input port coupled to the first test port, and an output port coupled to the bidirectional port. An inverter is coupled between the second test port and the multiplexer's second input port.
The invention also provides a method of improving detection of stuck-at faults in fault testing of an integrated circuit having a bus driven by a plurality of tri-state devices. In accordance with the method, the bus, which is coupled to a bidirectional port, is pulled down to a logic 0 value at the bidirectional port by applying to the bidirectional port, a pull down signal having a bus driving capability less than any of the tri-state devices' bus driving capabilities. A determination that at least one of the tri-state devices has a stuck-at fault is made if the logic value appearing at the bidirectional port during the pull down step is not 0. The bus is then pulled up to a logic 1 value at the bidirectional port by applying to the bidirectional port, a pull up signal having a bus driving capability less than a
Carr Larrie Simon
Iniewski Kris
Lapadat Curtis
Nakamoto Alan
Swic Monika
De'cady Albert
Lamarre Guy
Oyen Wiggs Green & Mutala
PMC-Sierra Ltd.
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