Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-10
1999-12-07
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714731, 327144, G01R 3128
Patent
active
060000511
ABSTRACT:
A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.-- In operation in all of the components concurrently at the rate of the Test Clock; performing the Update and Capture Operations in the first group of components at the rate of the Test Clock; and performing the Update and Capture Operations in the second group of components at the rate of the system Clock. The method employs a novel integrated circuit, test controller and boundary scan cells.
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Y. Zorian et al., "An Effective Multi-Chip BIST Scheme", Journal of Electronic Testing: Theory and Applications 10, (1997), pp. 87-95.
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IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990 (Includes IEEE Standard 1149.1a-1993) pp. 1-1 to 1-5; 5-1 to 5-16.
Cote Jean-Francois
Nadeau-Dostie Benoit
Klivans Norman R.
Logic Vision, Inc.
Tu Trinh L.
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