Method and apparatus for low overhead circuit scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S729000

Reexamination Certificate

active

07047468

ABSTRACT:
A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.

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Hans Jacobson, et al.,Synchronous Interlocked Pipelined CMOS, IBM Corporation, pp. 1-12.
Eric Mercer, et al.,Stochastic Cycle Period Analysis in Timed Circuits, Electrical Engineering Department—University of Utah, pp. 1-4, Salt Lake City, Utah.

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