Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-28
2002-09-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06453436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the testing and diagnosing of integrated circuits. More particularly, the present invention is directed to testing and diagnosing latch based scan chain defects and localizing these defects to a particular shift register latch. The present invention also provides a method and apparatus for enhancing test pattern generation for detecting delay defects.
2. Technical Background
The level-sensitive scan design (LSSD) and generalized scan design (GSD) test techniques (or simply scan design test techniques) enable testing at all levels of very large scale integrated (VLSI) circuit packaging. The circuit implemented on a chip using these techniques typically comprises several combinatorial logic blocks, each of which is associated with a storage cell consisting of a latch called a shift register latch (SRL). A single long shift register (SR), termed an LSSD chain, is formed by chaining a number of such cells or SRLs together. Each SRL, which is actually a pair of bistable latches designated L
1
and L
2
, forms a single stage of the shift register.
The L
1
latch can be set from two sources by two different clock signals, A and C, applied to clock inputs A and C, with the latter input receiving system clock signals. Latch L
1
also has a data input (DI) and a test input called scan data in (SDI). Test patterns consisting of binary bit vectors are applied to the SDI pin of the chip. Latch L
2
has a data input connected to one of the outputs of the associated L
1
-latch and an input that receives B clock signals causing the output data from L
1
to be transferred into L
2
.
The long shift register (SR) referred to above is formed by connecting the output of the L
2
latch in the first SRL (forming the first stage of the shift register) to the SDI input of the L
1
latch in the next SRL, and so on, down to the last SRL. The test input SDI of the L
1
latch in the first SRL is connected to the SDI pin of the chip, and the output of the L
2
latch in the last SRL is connected to an output pin, designated the scan data out (SDO), of the chip. The A, B and C clocks of the SRL are connected to the chip pins so designated. Bits are transferred through the SRL in two steps. A bit applied to the test input SDI of latch L
1
is loaded therein by the A clock pulse, and the same bit is obtained at the output of the L
2
latch at the occurrence of the B clock pulse. A number of pairs of A and B clock pulses equivalent to the number of SRLs is required in order for a signal applied to the SDI input of a functional element to be transferred to the SDO output thereof. In this mode of operation, clock C is not pulsed.
To test a functional element, one portion being a scan path, a static test called a “flush” test is first performed. To this end, an active potential, for example a high logic level, is applied to the A and B clock inputs (A=B=1) while the C clock input receives a low logic level (C=0). A square pulse is applied to the SDI input of the chain to be tested and is retrieved at the SDO output after a predetermined time interval has elapsed. A typical SR chain may consist of numerous inversion steps. As a result, the data pulse applied to input SDI is obtained at output SDO of the chain after a time interval equal to the accumulated response times of all the SRLs in the chain has elapsed. In addition to providing useful information on the propagation times, the flush test determines whether the LSSD chain is functioning properly.
A dynamic test called a “scan” test is next performed. In this test, the C clock is maintained at a low logic level while pulsing the A and B clocks. The LSSD chain then acts as a shift register. This test serves to establish that the chain is not operating properly if the data pulse applied to the SDI input fails to be transferred to the SDO output when an appropriate number of clock pulses are applied to the A and B clock inputs.
A functional test is then performed in the scan mode. In this test, a test pattern (a series of binary data) is applied to the SDI input and the A and B clocks are pulsed to transfer the test pattern into the SRLs. All the latches in the functional element having thus been initialized, logic data are present on the parallel output pins of the chip. By applying stimuli to the parallel output pins of the chip and pulsing the C clock, a binary vector reflecting some particular state of the combinatorial logic is loaded in the LSSD chain. The output pins and SRL states are then observed to determine if the combinatorial logic is functioning properly as compared to the expected states determined by a computer simulation model.
The basis for logic built-in self-test (LBIST) and array built-in self-test (ABIST) methodology is to generate product test vectors in order to detect potential faults in the product while the output responses are measured at primary outputs (POs) or captured into a multiple input shift register (MISR). In the diagnostic mode, the strategy is to scan out and observe each response that will be captured into the MISR signature, rather than one scan out of the MISR signature at the end-of-test.
A manufacturing defect in a semiconductor chip may cause a stuck fault, where an input or output of a circuit is stuck at a single logic value. An object of the present invention is to increase diagnosability of stuck faults located in the scan chain. In the introduction of a new semiconductor process, scan chain diagnostics become a very useful vehicle for yield learning. However, diagnosing scan chain stuck faults with present methods is neither simple nor guaranteed. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process problem. It is therefore desirable to modify the scan chain and provide a fast way of locating scan chain stuck faults which is also suitable for automation.
Another type of defect may cause the switching time of a circuit to become abnormally slow. This is known as a delay or transition fault. As, semiconductor technology has become more miniaturized, the incidence of transition fails caused by delay defects has increased dramatically. There are a number of mechanisms involving wire opens or partial opens that can cause excessive path delay. In order to maintain acceptable product quality levels of large multi-chip modules, high delay test coverage is usually required. Delay test coverage is generally lower than stuck fault coverage because delay tests must use two test patterns in order to define a transition. One factor limiting delay test coverage is that the latch settings required to cause a transition often conflict with the latch settings to propagate that transition. As an example, to test a 2-way AND circuit for slow-to-rise faults on an input, that input must have a logic 0 to logic 1 transition while the other input is held at 1. If both inputs to the AND circuit are driven by SRLs adjacent in the scan chain that pattern is not possible. The 0 to 1 transition on one input will cause the final state of the other input to be 0, thus blocking the transition from propagating to an observable location. This is the well known latch adjacency or correlated latch problem. Other techniques using multiple time image test generation have been used to solve this problem. Those algorithms, however, are significantly slower and the subsequent test patterns are less diagnosable. Accordingly, it is desirable to provide an apparatus and technique for solving the problems associated with circuit testing. It is further desirable to provide a solution for testing two input AND gates (as well as NAND, OR, and NOR gates) and significantly improve the testability of the multiple input functions using single time image algorithms.
SUMMARY OF THE INVENTION
According to the teachings of the present invention a 1:2/2:1 multiplexor (MUX) placed between every pair of SRLs. The one output/input from/to the MUX feeds directly to/from the scan port of adjacent
Rizzolo Richard F.
Song Peilin
Augspurger Lynn L.
Chase Shelly A
De'cady Albert
LandOfFree
Method and apparatus for improving transition fault... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving transition fault..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving transition fault... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2817193