Method and apparatus for high update rate integrated circuit...

Details Method and apparatus for high update rate integrated circuit... Method and apparatus for high update rate integrated circuit...

2006-05-02

2006-05-02

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07039840

ABSTRACT:
Boundary scan cells for driving internal logic and sensing internal logic of integrated circuit use external clocks synchronized with internal functional clocks. Synchronized clocks enable synchronous sampling of internal signals and synchronized of injection signals into a functional portion of the integrated circuit.

REFERENCES:
patent: 6173428 (2001-01-01), West
patent: 6785854 (2004-08-01), Jaramillo et al.
patent: 2001/0037480 (2001-11-01), Whetsel

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