Method and apparatus for high speed IC test interface

Details Method and apparatus for high speed IC test interface Method and apparatus for high speed IC test interface

2005-02-22

2005-02-22

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

06859902

ABSTRACT:
A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

REFERENCES:
patent: 4984161 (1991-01-01), Hayashi
patent: 6327678 (2001-12-01), Nagai
patent: 6446228 (2002-09-01), Kobayashi
patent: 6532561 (2003-03-01), Turnquist et al.
patent: 6557128 (2003-04-01), Turnquist
patent: 6557133 (2003-04-01), Gomes

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