Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-29
2002-09-03
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06446229
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to failure detection, and specifically to a method and apparatus for failure detection within an integrated circuit device utilizing an integrated flip-flop capable of supporting two test modes of operation.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device. Modem integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as a manufacturing defect may prevent the IC from performing all of the functions that an IC is designed to perform. Such demands require verification of the design of the IC and also various types of electrical testing after the IC is manufactured.
However, as the complexity of the IC increases, so does the cost and complexity of verifying and electrically testing each of the devices in the IC. Electrical testing ensures that each node in a VLSI circuit functions properly. Therefore, each node needs to individually, and in conjunction with the other node in the IC, function properly in all possible combinations of operations. Typically, electrical testing is performed by automated testing equipment (ATE) that employs test vectors to perform the desired tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every package pin during a period of time, often in an attempt to “test” a particular node. For complex circuitry, this may involve a large number of test vectors and accordingly, a long test time.
One way to address this problem is through design for test (DFT). The key concepts in DFT are controllability and observability. Controllability is the ability to set and reset the state of every node in the IC. Observability is the ability to observe either directly or indirectly the state of any node in the IC. The purpose of DFT is to increase the ability to control and observe internal and external nodes from external inputs/outputs.
DFT methods utilize various test circuits. One type of test circuit is a scan path or a scan loop in the logic circuit. A scan path or scan loop comprises of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. Typical scan circuit designs involve two or more separate scan paths or scan loops. For example,
FIG. 1
illustrates a prior art circuit with flip-flops in two separate scan paths, one scan path for snapshot mode of operation and one scan path for scan mode of operation. A first scan path is formed by shadow flip-flops
102
and
104
and an output is labeled snapshot_do
110
. A second scan path is formed by flip-flops
106
and
108
and an output is labeled scando
120
. This circuit design with multiple flip-flops for separate scan paths increases design complexity because of the increased routing and power consumption requirements.
The scan latches can be loaded with a serial data stream of scan vectors that set the logic circuit nodes to a predetermined state. The logic circuit then can be operated in normal fashion and the result of the operation is stored in its respective latch. A scan out operation serially unloads the contents of the latches and the result of the test operation at the associated nodes is analyzed for improper node operation.
Another DFT feature is a snapshot. A snapshot allows latching a state of the IC during normal operation, rather than scan vectors that initialize the integrated device to a particular state. The snapshot feature is helpful in debug analysis of computer system to insure integrity of the system hardware and software. The snapshot feature allows observability of internal nodes within the system to verify functionality.
The snapshot feature is triggered in a variety of methods. For example, a particular data signature generated by internal logic or an external event such as an external pin of the IC triggers a snapshot operation. The contents of the snapshot latches are unloaded via a test port. One example of a test port is a defined by the Institute of Electrical and Electronic Engineers(IEEE) is a Joint Test Action Group (JTAG) test protocols set forth in IEEE standard 1149.1. In such a system, a JTAG test device is connected to a pair of ICs or to a single IC. The JTAG device generates test commands for testing the ICs. Input and output of JTAG test commands is achieved through a set of JTAG-dedicated pins provided on each IC to be tested. Typically, the JTAG test device is employed to perform a boundary-scan test. The JTAG test commands for the boundary-scan test are adapted for testing the interconnections of ICs and are not typically well suited for testing or monitoring the internal logic of a IC. General information regarding JTAG and boundary-scan test strategies and implementations may be found in “Boundary-Scan Test, A Practical Approach”, by Harry Bleeker, Peter Van Den Eijnden and Frans de Jong, Kluwer Academic publishers 1993.
REFERENCES:
patent: 5459735 (1995-10-01), Narimatsu
patent: 5488614 (1996-01-01), Shima
patent: 5689517 (1997-11-01), Ruparel
patent: 6181179 (2001-01-01), Kanba
Merrick Dale F.
Priesnitz Joachim
Chung Phung M.
Intel Corporation
Nesheiwat Michael J.
LandOfFree
Method and apparatus for integrated flip-flop to support two... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for integrated flip-flop to support two..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for integrated flip-flop to support two... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2883292